praveen pandey

Worked on all the aspects of Synthesis, Physical Design and Signoff including Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction, Timing Closure, Power / IR Drop (Static), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS) and DFM. Tools: Genus, Innovus/ Encounter, Spyglass Constraints checker, Tempus, Calibre, Voltus, StarRC

Worked as a part of deployment team to provide technical support for users of Olympus/Nitro-SoC (Mentor Graphics complete digital implementation system for advanced-node ICs and SoCs). Providing custom scripts, design flows and detailed tool diagnostics for digital physical design at advanced nodes (28nm, 16nm, 10nm, 7nm). Specialties: Strong physical design, analysis and debug experience. Responsibilities included: Implementation (PnR) of multimillion gate SoC designs in cutting edge process technologies (28nm, 16nm, 10nm & 7nm) using Nitro-SoC. All aspects of Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY. Innovate on the flows to meet the QoR targets and ensure predictability using Nitro-SoC Exposure to the latest design rules, processes and innovations need to close PPA on the advance nodes.

“Worked On AMBA & I2C Bus Design and Verification”, “FPGA Implementation” & “Physical Design & Verification”

* Worked on 4 projects from schematic level to layout with Electronics Corporation of India Limited (Government of India Enterprise) under Computer Education Division titled * gt * Physical Design & Analysis of Low Voltage Operational Amplifier * gt * 8-bit ADC * gt * Design of Small Signal LNA * gt * RISC based 32-bit general purpose microprocessor in Verilog