Pravalika Pannala
DFT Engineer @ Mirafra Technologies
India
Hyderabad
Semiconductors
Scan Insertion, Automatic Test Pattern Generation (ATPG), Tessent Shell , TestKompress, Fastscan
Experience
DFT Engineer
Mirafra Technologies
Banglore
Working on Scan Insertion , ATPG and Simulations and QSCAN Flow.
Design Engineer
ChipSil Technologies Pvt Ltd
Hyderabad Area, India
Worked on Scan Insertion , Pattern Generation coverage debug and Simulation , Stuck-at ,at-speed pattern generation. Had exposure on simulating the ATPG Patterns. Tools : Tessent Shell , FastScan , TestKompress
Pravalika Pannala's Contact Information
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