Prashanth K V

Senior Emulation and FPGA Prototyping Engineer @ Analog Devices

Country

India

City

Bengaluru

Industry

Semiconductors

Skill

IAR Embedded Workbench, RTL Design, FPGA Design, Emulation and FPGA Prototyping, Field-Programmable Gate Arrays (FPGA), Very-Large-Scale Integration (VLSI), Digital Electronics, Verilog, Intel Quartus Prime, Xilinx Vivado, RTL Coding, Emulation, FPGA prototyping, NCSim, Synopsys Protocompiler, Xcelium Simulator, HAPS, Synopsys Verdi

Experience

Senior Emulation and FPGA Prototyping Engineer

Analog Devices

2026-3 - Present · 7 mos

Bengaluru, Karnataka, India

FPGA Prototyping: HAPS 100

Senior FPGA Engineer

SiSoC Semiconductor Technologies Pvt Ltd.

2025-4 - 2026-3 · 1 yr

Bengaluru, Karnataka, India

FPGA Prototyping Client: NXP Semiconductor

VLSI Engineer

Wipro

2021-6 - 2025-4 · 3 yrs 11 mos

Bengaluru, Karnataka, India

FPGA Prototype developed for ASIC SOC, focused on building Synopsys HAPS model based on SOC RTL inputs and integrating interfaces/IP’s as required. ASIC-to-FPGA conversion including RTL Modification, Memories, Clocks and optimisation. Defining Synthesis, P&R Strategy’s for better area and performance. Running sanity tests and release Bitfile to consumers. Supported Prototype users with bring-up, debug, integration, enabling seamless cross-functional team collaboration in pre-silicon environment. Tools & Tech: HAPS 80 hardware, IAR, Segger Jlink, Synopsys VCS and Verdi, Cadence Simvision, Synopsys Protocompiler, SOC, Perl Scripting, Verilog, System Verilog, VHDL, Embedded C, I3C, DDR3.

Associate Engineer

Rangsons Aerospace Pvt Ltd

2020-7 - 2021-6 · 1 yr

Bengaluru, Karnataka, India

Design and Verification of FPGA Based IP core. Implemented RTL Code for FPGA Design, developed FPGA flow from RTL to Bit stream generation. Tools & Tech: Verilog, System Verilog, Xilinx ISE, ILA, Xilinx Vivado, Quartus Prime, ModelSim, Testbench, Oscilloscope, Logic Analyzer, Spartan 6, Xilinx Virtex 7, Altera Max 10, UART, I2C, SPI