Prakshi Rastogi

• Led physical design of compute-intensive blocks for cutting-edge Cloud TPUs, driving them from synthesis and placement through ECOs to successful tapeout. • Owned physical design for networking chip blocks, taking them through synthesis and placement. • Expertly managed timing closure (STA) and equivalence checking (LEC) to ensure design integrity and performance. • Collaborated with architecture and design teams to implement requirements and achieve optimal PPA on advanced ASIC technology nodes. • Worked with RTL team on design tradeoffs for efficient physical design closure.

• Delivered multiple ML compute blocks for Google Pixel Edge TPU, successfully taking designs from physical implementation to tapeout. • Optimized designs in collaboration with RTL engineers to meet stringent power and performance targets for mobile applications. • Pioneered and implemented VCLP methodology across an entire IP. • Proficiently utilized equivalence checking (LEC), static timing analysis (STA), and extraction (StarRC) tools. • Developed and refined physical design methodologies and automation scripts, enhancing flow quality and efficiency. • Worked on the physical implementation of ASICs using advanced technology nodes, contributing to top-level/block-level timing analysis and ECO generation.

• Implemented Primetime Eco on partition and full chip level and did ECO fixing. • Owned partitions and implemented PD flow on them and signed them to review. • Worked on the Static Timing Analysis and devised solutions to meet timing criteria and formulated scripts in Perl and TCL to make flow automated.

-Worked as a Physical Design Intern -Implemented Physical Design flow( From synthesis to Apr) for SOC's - Worked on Formal Equivalence(FEV) and proving equivalence between the RTL netlist and the gate level netlist -Static Timing Analysis-Analyzing Timing reports and debugging them for Timing violations(Setup timing, hold timing) - Developing scripts in Perl, Shell to automate the Physical design flow

Projects Done: ---Reconfigurable Architecture for Machine Learning Acceleration Fall ‘17 Increasing the performance of Deep Neural Networks/Convolutional Neural Networks by using VLSI architecture and performing the layouts of the architecture --- Design and Implementation of a 45nm 6-T SRAM and Arithmetic Unit: Advanced VLSI Fall ‘16 • Implemented a pipelined system of a 64 byte 6T SRAM, circuit to drive a 150fF capacitive interconnect in Cadence Virtuoso ---Implementation of Bounded PRIM and BRBC routing algorithms using C++: Physical Design & Automation Fall ‘16 • Developing a model that efficiently routes the entire circuit by decreasing both its wirelength and cost at the same time. Developed a new Algorithm that reduced the radius upto 35.2%.