Piyush Kasera
Silicon RTL Design Engineer III @ Google
About
Chip design enthusiast working as RTL designer on developing custom silicon for Google Cloud. Completed my master's in computer engineering and have 4+ years of experience in ASIC/FPGA RTL design and micro-architecture. Well-versed in C/C++, Verilog and System Verilog. Having in-depth knowledge and hands-on experience in bringing up Emulation compatible RTL models, ASIC/FPGA micro-architectures, RTL design/integration, and logic synthesis with optimizations for best PPA metric acquired through academic projects, relevant coursework and work experience. I always strive for excellence in all my fields with a strong desire to learn new design concepts and technology ideas that would help me learn, create and simultaneously contribute towards my organisation's short and long-term goals.
United States
Sunnyvale
Semiconductors
Programmable Logic Controller (PLC), Kalman filtering, Matlab, C, Microsoft Word, Autocad electrical, Verilog, Microsoft PowerPoint, Microsoft Excel, Electric Vehicles, NI Multisim, Automotive Electrical Systems, Arduino, SCADA, Electrical AUTOCAD, Unix, TCL
Experience
Silicon RTL Design Engineer III
Sunnyvale, California, United States
Silicon RTL Design Engineer II
Sunnyvale, California, United States
Involved in custom AI/ML silicon development for Google Cloud.
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Mesra
Event coordinator at EEESOC, BIT MESRA.
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Kharagpur Area, India
PLC and SCADA
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Kolkata Area, India
Education
University of Southern California
Computer Engineering
Specializing in Digital VLSI and Computer Architecture. Coursework:- EE457: Computer System Organization (Coursework on CPU Performance, FIFOs for Clock Domain Crossing, Pipelined CPUs, Cache Coherency, Out-of-Order Execution, Multi-core Multi-threaded processors) EE477: MOS VLSI Design (Coursework on VLSI basics, digital MOS and course project on layout of ALU unit including MAC, adder and multiplier) EE557 - Computer Systems Architecture (Pipelined processors, speculative execution, VLIW, vector processors, GPU/GPGPU, interconnection networks, shared-memory and message-passing multiprocessors, Chip Multiprocessors) EE577A: VLSI System Design-I (Projects include 512-bit 4-bank SRAM custom layout, In-memory compute operation using 10T SRAM) EE577B: VLSI System Design-II (Project includes RTL Design of Bidirectional Ring NOC router and Chip-Multiprocessor system and running flows including Synthesis, LEC, STA, PNR) EE581 - Mathematical foundations for System Design and Analysis.
Piyush Kasera's Contact Information
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