Patrick La Fratta

Senior Staff Modelling Engineer employed by Prodapt, currently on assignment at Meta

Lead technical role for simulation-based memory hierarchy performance analysis and optimization for a heterogenous multicore processing system. • Utilized the Structural Simulation Toolkit (SST) to calibrate a DRAMSim3-based HBM memory model with third party data to measure performance sensitivity to tRRD and improve model accuracy. • Lead the establishment and maintenance of multiple toolchains and multithreaded HPC benchmarks for simulation and performance analysis. • Hand-tuned assembly code of a multithreaded STREAM kernel for target architecture to achieve ∼10x improvement in bandwidth. • Delivered detailed reports of benchmarks and utilities, including CLOMP, EPCC, and perf, as candidates for performance analysis toolset.

Technical lead for Advanced System Architecture team’s external memory controller model collaborative development efforts. • Lead the collaborative development effort with ASIC Modeling team for an LPDDR5 memory controller model. • Planned and scheduled code development for the model. • Lead and contributed to the delivering of extensive test data to demonstrate model correctness and alignment with specifications.

Technical lead for Advanced System Architecture team’s internal memory controller model development. • Planned and lead a ground-up implementation of an optimized version of a memory controller model in SystemC. - The new model achieved an average of 2.5x geometric mean speedup and approximately 100x maximum speedup over the previous version. • Architected a framework in Python for testing this memory controller model. - Leveraged this test framework to write several hundred synthetic and directed tests for the controller’s large feature set, which included multiple scheduling policies (e.g. FRFCFS and FRFCFS with read priority), address map customization for tuning bandwidth and latency, open/close page modes, various refresh modes, adjustment of numerous queue and buffer sizes, and many others. • Implemented support for various devices in this controller model, including DDR3, DDR4, DDR5, LPDDR5, HBM2, HBM3, and 3D XPoint. • Conducted analyses and delivered data on the sensitivity of various workloads’ execution time to bandwidth and latency of the memory system.

Contributed to the design and performance evaluation of a high-performance DRAM device utilizing disruptive technology. This work involved analyses of data derived from simulation-based and hardware-based experimentation to gain insights into tradeoffs of design alternatives for various operations on the DRAM device and its associated memory controller. Data were presented in terms of bandwidth, latency, and application execution time for various kernel benchmarks to better understand impacts of changes to DRAM device design parameters. A study of the implications of changes to address bit mappings on the memory usage of the Linux operating system was completed through full system simulation.

Instructor for CS 441, Computer Architecture. Member of Thesis Proposal Committee for Gregory Cook. Thesis title: "Post Register Allocation Modulo Scheduling for the ARM Cortex-A8 Processor."

Designed hardware/software system and simulation environment for verification of device compliance with the Remote Readiness Asset Prognostic/Diagnostic System (RRAPDS) Communications Protocol for Health Monitoring Systems (HMS) under the Stockpile Reliability Program. Conducted research in the design and evaluation of high-performance, energy-efficient parallel processor architectures. This research included contributing to a group study for the optimization of processing hardware for the Integrated Hostile Fire Detection System (IHFDS). Served as technical evaluator for Small Business Innovation Research (SBIR) proposals offering techniques for verifying security in ASIC and FPGA designs. Supported the Joint Land Attack Cruise Missile Defense Elevated Netted Sensor (JLENS) project with expertise in hardware and software, with work including investigations into peformance tradeoffs for signal processing on general purpose processors.

Dissertation Title: Optimizing the Internal Microarchitecture and ISA of a Traveling Thread PIM System Advisor: Dr. Peter M. Kogge - Conducted research in computer architectures based on emerging processing-in-memory fabrication technology. - Performed design explorations and performance evaluations of the ISA, microarchitecture, execution model, and code generation tools. - Code development, analysis, and testing for this project required extensive use of C++ programming for microprocessor simulation, bash scripting, gnuplot, Dot, Dia, and Excel. The Sun Grid Engine (SGE) and the Condor high throughput computing system were both used for processing large-scale simulations over clusters of PCs connected over a LAN. Also utilized MATLAB for tradeoff analysis in successive processor fabrication technology generations.

Designed and implemented the parallel Discrete Fourier Transform (DFT) for an x86-based microprocessor with Tesla C1060 GPU using the CUDA programming language, a C++-based language written for programming NVIDIA's state-of-the-art computing devices. Also conducted performance evaluations and optimizations for the parallel DFT on the C1060, which required research into the DFT algorithm and C1060 hardware design. My work on the acceleration of the Fourier Transform was performed in support of the cruise missile defense system project JLENS (Joint Land Attack Cruise Missile Defense Elevated Netted Sensor System) at Redstone Arsenal.

Proposed two innovative microprocessor designs for accelerating scientific applications at Sandia National Labs (SNL). The applications included SNL's CTH: a shock-wave physics computer code used in various aspects of weapons and armor systems evaluation including warhead design, explosion physics, and safety issues; ALEGRA: a family of multi-physics codes for simulating large deformations and strong shock physics for the development of advanced armor concepts; the LAMMPS molecular dynamics code; and others. Planned and scheduled the simulator development for the proposed microprocessor designs, developed models of the designs in C++ based on Sandia's Structural Simulation Toolkit (SST), and performed hardware and software evalutions using the developed models. The evaluation required extensive use of the Sun Grid Engine (SGE) to manage batch simulation jobs to a PowerPC-based cluster environment. The authoring of the simulator required extensive use of linux-based code development and source control tools, including makefiles, the GNU C++ compiler (g++), GNU debugger (GDB), and the Subversion revision control system (SVN). My work on this project involved collaboration with Senior Members of the Technical Staff at SNL highly experienced in the field of computer architecture. They assisted me in authoring two papers presenting the designs, evaluation results, and analyses of the proposed microprocessors.

Assisted in the development of an FPGA-based system optimized to run the Smith-Waterman algorithm for genome sequencing. My contribution to this product entailed the planning and scheduling of a code development project to interface a web-based frontend to the FPGA device using the C and C++ programming languages. The code development efforts required the use of network programming to interface the microprocessor to the server connected over a LAN running the user interface. The SVN source control tool, the gprof profiler for software evaluation, Bugzilla for bug tracking, and GDB were also used extensively. Knowledge of the FPGA design was required to transfer data from on-board memory to the FPGA device for efficient query processing.

M.S. Thesis Title: Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology Advisor: Dr. James. M. Baker, Jr. - Conducted research in the design, modeling, and performance evaluation of SCMP, a Single-Chip Message-Passing parallel computer system. - Designed and developed a new SCMP software-based model using a system-level modeling language, SystemC, implemented as a set of libraries to the C++ programming language. Managed software revisions using the CVS software control tool.

- GTA for ECE 1574: Engineering Problem Solving with C++. - Assisted in the instruction of freshman engineering students seeking admission to the Department of Electrical and Computer Engineering. - Worked closely with students in both office hours and lab environment, assisting in the development of problem-solving skills and programming practices. - Code development in this course was conducted through Microsoft Visual Studio. This required close familiarity with and frequent usage of Visual Studio in order to instruct students in project completion.

Dissertation Title: "Optimizing the Internal Microarchitecture and ISA of a Traveling Thread PIM System" Advisor: Prof. Peter Kogge Full Text Available Online: https://doi.org/10.7274/hh63st76m6h

Thesis Title: "Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology" Advisor: Prof. Mac Baker Full Text Available Online: http://hdl.handle.net/10919/32424

Cum Laude, With Honors in Engineering.