Patricia Fong
Director @ Marvell Technology
United States
Cupertino
Design
Static Timing Analysis, Timing Closure, Tcl-Tk, ASIC, Project Management, Perl, Integrated Circuit Design, Primetime, Timing, Hardware Architecture, VLSI, EDA, TCL, FPGA
Experience
Director
Marvell Technology
Senior Principal Engineer -Timing
Marvell Technology
Custom Compute & Storage Senior Staff Manager
Marvell Technology
Santa Clara, California, United States
West Coast ASIC Design Center Manager
Marvell Technology
Principal Engineer, Physical Design - Timing
Marvell Technology
ASIC Design Engineer
GlobalFoundries
Lead timing engineer, interface with customer and their design, timing runs and constraints, work with other timing engineers and coordinate work
ASIC Design Engineer
IBM
Lead timing engineer, interface with customer and their design, timing runs and constraints, work with other timing engineers and coordinate work
Xbox Hardware Design Engineer
Microsoft
Develop a device to simulate an environment where the product would be running at a higher temperature.
IC Design Engineer
Agere Systems
Work with Primetime and timed portions of a chip.
Education
Duke University
Management
University of California, Berkeley
Electrical Engineering and Computer Science
Patricia Fong's Contact Information
Phone
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