Hoon Park

Research topics: -Adopting Full-Empty protocol, separating asynchronous components in to joint (where computation happens) and links (where data is stored) makes them interchangeable between different circuit families. This brings translation-free communication between different self-timed circuit families. -Identifying timing constraints and verification of individual link and joint -Modeling and verification of Metered Merge, Bounded Response Time Stack, etc. -Relative-Timing constraint analysis in Synopsys Design Compiler -Hands-on with 40nm CMOS test chip. Used JTAG, Scan features to characterize test chip -Exploring applicability of asynchronous design methodology in Artificial Neural Network

Modeling and verification of Relative-Timing constraints for delay-insensitive designs, Asynchronous Research Center (ARC). Before joining the ARC, I also worked on developing tutorials and graduate level projects for the Veloce Hardware Emulator.

Recitation class for: ECE171 Digital Circuits. Grading TA for: ECE271 Digital Systems, ECE341 Computer Hardware, ECE483 Low Power Digital IC Design.

Developed and performed regression tests for Veloce2 emulator.

Maintained training support materials and unit training calendar for the 2nd Battalion 9th Infantry Division Charlie Company. Assisted soldiers with administrative paperwork. (English, attention to detail, and record keeping is important.)

Computer architecture, Formal verification, Modeling and Analysis of Embedded Systems