Parin Senta

Accelerator Design

EECS 570: Parallel Computer Architecture

High-Performance Course Grained Reconfigurable Architecture Advisor: Prof. Blaauw and Prof. Kim

EECS470: Computer Architecture

• Designed a 16-bit Multi-Cycle Memoryless Processor with custom RISC ISA, interrupt support, and low power mode capabilities to replace a design-specific hardware module for reprogrammability | Simulated on Cadence XCelium • Synthesized the new block with the processor, resulting in a ~10x area reduction compared to the ARM IP alternative

Local Inversion of Maps: Black-box Cryptanalysis • Investigated a novel black-box approach for computing the inverse of an encryption map using the minimal polynomial of recursive sequences defined by the map • Developed a highly scalable algorithm using NTL Library - a high-performance, portable C++ library, reducing the computation time by a factor of 40 • Utilised the algorithm for Chosen-Plaintext Analysis of RC4, DES, and RSA encryption methods

Selective Out-of-Order (OoO) Warp Scheduling in GP-GPUs • Reviewed literature on warp-scheduling and compiler-assisted OoO scheduling of instructions during stall cycles to explore ways to improve the performance of GPU through dynamic scheduling • Devised a novel strategy that considers instructions with false data dependencies as valid candidates for OoO scheduling, incurring hardware overhead of only 4 extra registers • Implemented two rounds of OoO warp scheduling and simulated benchmark suites from NVIDIA SDK on GPGPUSim - a cycle-accurate simulator, obtaining a performance gain of 12% over baseline

• Automated hierarchy generation of Hard Macros (HM) of any specified chip using Python to correct its die area as part of the SoC Synthesis Team, reducing 15+ man hours for the task • Showcased the hierarchy as an interactive HTML table to analyze variations in chip area due to changes in the instance count of HMs, particularly helpful in the area estimation of a derived chip • Implemented Synthesis Reference Flow to synthesize a small HM on Synopsys DC

• Explored the process of modelling and simulating junction devices to examine their electrical properties • Designed and simulated InGaAs PIN diode using Silvaco TCAD to test the effect of lateral temperature gradient at cryogenic temperatures on charge transport

Specialization: Integrated Circuits and VLSI

Minor - Computer Science