anil pandya

engineering executive | leading high performance vlsi design engineering teams

About

Location: San Francisco Bay Area; Industry: Semiconductors ... Summary. * I am a results-oriented executive with strengths in building and managing global organizations. ... DIRECTOR DESIGN ENGINEERING, Microprocessor Cores Functional Verification and scanDFT. AMD .... Assistant Vice President at Deutsche Bank.

Country

united states

City

san francisco

Industry

semiconductors

Skill

soc, functional verification, microprocessors, asic, computer architecture, verilog, semiconductors, vlsi, eda, systemverilog, engineering management, static timing analysis, project management, management, rtl design, physical design, silicon, cross functional team leadership, dft, c++, ic, simulations, cross cultural teams, integrated circuit design, perl, semiconductor industry, methodology, cad tools, vendor management

Experience

senior design technology engineer

imp

1986-1 - 1989-1 · 3 yrs 1 mo

Developed standard cell/block automatic placement and routing tools, using C on UNIX platforms.

director design engineering, microprocessor cores functional verification and scandft

amd

2006-1 - 2012-1 · 6 yrs 1 mo

senior manager design engineering, functional verification

amd

2003-1 - 2006-1 · 3 yrs 1 mo

Co-managed 60 engineer dual-site team delivering verification signoff for K8 RevG (65nm dual core Turion) per plan. Ramped and assimilated Boston verification team into program. Met challenging 9 month schedule from GDSo to production. Recognized for expedited completion of DeerHound RevA GDSo (65nm quad core Opteron, Phenom, Turion II) providing verification management support to Austin colleague while managing BullDozer core verification. Facilitated 3 month DeerHound production schedule pull-in through meticulous planning, focused engineering, calculated risk taking and prioritized decision making.

manager design engineering, functional verification and cad tools and methodology

amd

1999-1 - 2003-1 · 4 yrs 1 mo

Managed team of 25 engineers and provided technical leadership for functional verification of K8 RevA-F (130nm, 90nm dual-core Opteron, Athlon), including custom macro verification, CAD tools, design methodologies and system infrastructure. Organized dual-site team improving morale after significant attrition from K8 classic project during dot com boom period. Co-led team delivering critical K8 product cycle involving creative innovations; x86-64, HyperTransport, integrated NB-DDR2 memory controller, Virtualization, dual-core JackHammer. Hired engineers from India to work in CA during dot com boom. Established verification effort in Singapore and India design centers.

manager design engineering, cad tools and methodology

amd

1995-1 - 1999-1 · 4 yrs 1 mo

Managed and technically led 15 engineers in development, integration, support and expert use of a broad suite of CAD tools, design methodologies for K5-LP, K6 family, IronGate chipset, K8 classic projects. Developed creative methodology solutions and automated flows based on internal and vendor tools for schematic entry, logic synthesis, static timing (setup, hold, cycle steal, superlength, noise margin), LEC, formal property checking, library characterization, APR, custom layout entry, parasitic extraction, physical verification (DRC, LVS, ERC), repeater insertion. Built effective vendor relationships and established technology partnerships enabling seamless integration and co-existent use of different vendor tools in AMD environment. Managed large CAD tool budgets and executed creative key license negotiation agreements with EDA vendors enabling win-win relationships. Partnered with IT team delivering best performance and utilization per $$$ of the multi-site server farm, using LSF.

member of technical staff and engineering manager positions

sgi

1989-1 - 1995-1 · 6 yrs 1 mo

* Developed RTL, gate, fault simulation tools and microprocessor design methodologies used on R4x00 and R10000 projects. Managed, led 6 engineer team. * Established a RTL to GDS synthesis methodology using vendor, university and in house tools.

engineering executive | leading high performance vlsi design engineering teams

xilinx

2013-1 - Present · 13 yrs 9 mos

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3D ICs. Xilinx uniquely enables applications that are both software defined, yet hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT and 5G Wireless. To learn more visit www.xilinx.com