PADMATEJA MARATHU
GPU Design Verification Engineer @ Qualcomm
United States
Portland
Consumer Electronics
Verification and Validation (V&V), Linux, Vim, Constraint Randomization, MIPS Instruction Set, Functional Verification, Cache Coherency, Randomization, Object-Oriented Programming (OOP), Computer Architecture, Assertion Based Verification, Universal Verification Methodology (UVM), Verilog, Static Timing Analysis, Logic Design, SystemVerilog
Experience
GPU Design Verification Engineer
Qualcomm
San Diego Metropolitan Area
Working in the Shader Processor verification team: Developed constraints for the constant buffer in SP. Developed an automated flow for the coverage Reporting. Debugging the failure test cases and assisting with TB updates as needed.
Pre - Silicon Validation Intern
Intel
Hudson, Massachusetts, United States
• Worked on the fuses validation in the emulation environment for the Xeon Server chip. • Owned and validated various IP‑disable scenarios and found bugs in the process. • Created targeted and random test cases, assessing coverage, and debugging failure test cases.
Education
Portland State University
Electrical and Computer Engineering
R.M.D ENGINEERING COLLEGE
Electronics and Communication Engineering
PADMATEJA MARATHU's Contact Information
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