Omkeshwar Shukla

◦ Optimised GPU and DDR configurations on Snapdragon chipsets, achieving a 22% FPS uplift and 18% improvement in power efficiency across key mobile gaming workloads ◦ Built and automated in-house profiling tools, cutting GPU performance triage time by 70%, and enabled actionable insights for microarchitecture tuning ◦ Collaborated with RTL and architecture teams to correlate perf/power anomalies with cycle-accurate simulations, leading to 9% FPS gain on Vulkan/Dx12 workloads via targeted microarchitectural enhancements

◦ Build 5G Open-RAN architecture using Intel-based FlexRAN O-DU & O-RU (8T8R with low PHY) built by Analog Devices, to validate O-RU performance and analyzed EVM results for 1*100 MHz, 2*100 MHz, & and 10 other different use cases: ◦ Wrote scripts in Python & Bash to drive automation for faster verification & and shorter time to market (3 months of time saved) ◦Created extensive user guide and documentation, maintained 3 Confluence and bit-buckets pages

◦ Engineered the Next-Generation 5G Virtualized Distributed Unit Solutions that will deliver 30% of total operational savings ◦ Strategized the Software Update Manager for Integrated Management System for Next-Generation Distributed Units ◦ Curated and developed over 10 comprehensive technical resources for entry-level graduates, covering essential aspects of 5G Core Network, Beam-forming principles, MIMO, mm-wave communications, and Multi-RAT Dual Connectivity

◦ Mitigated chronic network problems by implementing corrective action plans for Orange affiliates, and major content providers (Apple, Amazon, Facebook, Google, GAIKAI, Microsoft), resulting in a 15% reduction in traffic disturbance ◦ Streamlined cross-functional collaboration, slashing guaranteed time to repair by 40% through effective coordination ◦ Authored 50+ impactful technical resources for entry-level graduates, elucidating network protocols (OSPF, BGP, MPLS) and fundamentals (OSI, IP, TCP, UDP, SD-WAN, routing, switching)

◦ Conceptualized a low power, 2-staged SAR ADC; sample rates less than 6 mega samples per second and resolution of 8 bits ◦ Orchestrated 20 % efficient architecture (8-bit SAR ADC) using Matlab SIMULINK

• Developed insight into mitigating faults introduced due to cosmic radiation in the bus controller (MIL-STD-1553B) • Implemented the Triple Modular Redundancy (TMR) algorithm in the 1553B controller core memory • Executed over 410 files (> 3000 lines of code) using Questasim and Xilinx, & analyzed waveform, and complied test benches (Deliverable: 1 IEEE INDICON-2019 (Conference))

Served as an Algebra Expert at Chegg Inc., supporting high school students globally in their Higher Algebra problems. Empowered students to succeed in Algebra by providing comprehensive explanations, step-by-step guidance, and effective problem-solving strategies.