Nithyashree Srinivasan

Nuvia CPU LSU Modelling and Performance Verification Skills: C++ · RTL · ARM Architecture

• Developed and enhanced low power design methodologies for leakage & dynamic power recovery and Vmin optimization. • Developed a utility to intelligently estimate the scope of leakage reduction with a quick TAT. This is used as a leakage sign-off methodology by SoC leads. • Worked on a Machine Learning based approach to predict the percentage leakage reduction in a design. • Developed a quick PrimeTime based Ring Oscillator to evaluate the performance/variation scaling of devices across technologies and hence recommend a power optimal frequency plan to the SoC leads.

• Led the designing of ring oscillators whose sensitivities to manufacturing variations co-relate with that of SRAM memories. This IP is used to track Vmin and thus set appropriate rail voltage for memories. • Recognized with a QUALSTAR award for developing a utility that is used across design teams to determine Vmin criticality and thus placement obligations of Core Power Reduction (CPR) sensors. • Proficient in Design and Characterization of Digital circuits.

• One year internship program during undergraduate studies. • Developed a tool to calibrate relays for minimizing voltage fluctuations. • Worked on an augmented reality project using Microsoft HoloLens, to control the relays using gestures.

VLSI I COMPUTER ARCHITECTURE HIGH-SPEED COMPUTER ARITHMETIC I PREDICTION MECHANISMS IN COMPUTER ARCHITECTURE OPERATING SYSTEMS PARALLEL COMPUTING PARALLEL COMPUTER ARCHITECTURE DATA SCIENCE LABORATORY PARALLELISM AND LOCALITY STATISTICAL METHODS II SUPERVISED TEACHING