Nilanjan G.
Principal Graphics Architect @ Qualcomm
About
Nilanjan is a Principal Graphics Architect at Qualcomm, where he works on next generation GPUs for virtual reality and augmented reality applications. He has over 16 years of experience in designing and optimizing 3D graphics pipelines for low power and high-efficiency mobile devices, using both tile-based and immediate mode rendering techniques. He is an expert in advanced rendering techniques, such as static and dynamic occlusion, and has delivered a novel architecture for 2D graphics rendering hardware, along with the specification, API, and test framework. He also has skills in image, audio, and video processing, and holds multiple patents and publications in the field of computer graphics. His mission is to create immersive and realistic experiences for users through cutting-edge graphics technology.
United States
San Francisco Bay Area
Research
Computer Architecture, Computer Graphics, C++, C, System C, Algorithms, GPU, CUDA, GPGPU, Microarchitecture, Processors, Python, Perforce, Hardware Architecture, Optimization, Digital Signal Processing, Teaching, Multi-core, Vim, Compilers
Experience
Principal Graphics Architect
Qualcomm
Santa Clara, California, United States
- As a member of Graphics Research Team (GRT), working on next generation Qualcomm GPUs.
Review Panel Member
National Science Foundation (NSF)
Alexandria, Virginia, United States
Graphics Architect
Meta
Sunnyvale, California, United States
Worked as a graphics pipeline architect at the Meta Reality Labs (https://about.fb.com/news/2024/09/introducing-orion-our-first-true-augmented-reality-glasses/) on the following items: * Proprietary hardware display pipeline architecture for Meta Orion Glass project * Built an end-to-end graphics rendering architecture model for graphics hardware for Meta Orion Glass project * As a lead architect delivered an architecture for novel 2D graphics rendering hardware for Meta Orion Glass project ** Delivered architecture specification, software interfacing/API architecture, test case generation framework ** Supported entire team until design completion ** Coded an architecture model for the above item * Worked on static and dynamic occlusion for AR/VR systems
GPU Architect (Advanced Computing Lab)
Samsung Electronics
San Francisco Bay Area
- Similar amount of time spent on the following items: * Research/design/development of a power and performance efficient 2D hidden surface removal algorithm for mobile graphics architecture. * Performance and power-optimized vertex attribute fetch architecture proposal for the geometry pipe of the mobile graphics pipeline; including graphics driver optimization for the same. * Worked on end-to-end graphics benchmark generation process for the exploration/comparison of the alternative graphics architecture proposals for emerging areas and platforms. * Exploration of a power-performance co-optimized attribute interpolator architecture for the mobile graphics platforms.
GPU Architecture Engineer
Apple
Orlando, FL
- In the decreasing order of time spent. * Worked on fixed-function pixel pipe (bitstream parser, setup, and rasterization) of the graphics pipeline. * Worked on mutual exclusion block of the graphics shader core architecture. * Worked on primitive binner logic of the fixed-function geometry processing of the graphics pipeline.
Doctoral Researcher (Computer Architecture)
University of Florida
Gainesville, Florida
Pursued graduate research on power efficient throughput architecture design and analysis at the department of Electrical and Computer Engineering.
GPU Architecture Intern
NVIDIA
San Francisco Bay Area
GPU microarchitecture optimization.
Compiler Engineer (Intern)
Texas Instruments
Houston, Texas Area
Worked on OpenMP compiler design for existing c6000 series of compilers. Primarily worked on parsing of the following constructs and clauses: omp for, shared, num_threads, private, firstprivate, lastprivate, nowait, single.
Communication Infrastructure Development Engineer (Intern)
Texas Instruments
Germantown, MD
Worked with multi-core DSP and codecs. 1. Designing novel algorithm for H.264 CABAC encoding on multicore processors (Tomahawk) 2. Implementation of assembly routines (written in c64x assembly language) for different syntax element encoding on Tomahawk and testing using self test bench
Senior Member of Technical Staff
Interra Systems
Kolkata Area, India
Worked with Embedded Systems and Codec Development Group. 1. Bitstream editor for CABAC encoding support in Vega H.264 analyzer 2. CABAC encoder and motion estimation algorithm optimization for B-frames of H.264 encoder of Texas Instruments Inc
Member of Technical Staff
Interra Systems
Kolkata Area, India
Worked on design, development and optimization of audio codecs. 1. AAC-LC audio codec reference code development for TI Da Vinci series of DSPs 2. SBR module reference development for TI Da Vinci series of DSPs
Education
University of Florida
Computer Engineering
Graduated with PhD in Computer Architecture. Dissertation title: "Power-performance co-optimization of throughput architecture using emerging technologies."
University of Florida
Computer Engineering
Kalyani Government Engineering College
Electronics and Communication Engineering
Graduate with Bachelor of Technology in Electrical and Communication Engineering.
Nilanjan G.'s Contact Information
Phone
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