Nikhil Reddy M.

1. Performing power projections for voltage-frequency (VF), noise (di/dt), electrical design point (EDP), to set plan of record (POR) specs for the future line of NVIDIA products. 2. Drive HW/SW co-design by architecting pre-silicon di/dt noise mitigation features that maximize sustained clock frequencies during bursty, dense workloads. Profile dynamic voltage/current transients to optimize the Power Delivery Network (PDN) against worst-case algorithmic test profiles. 3. Review chip design timing (setup/hold) corners across netlist milestones to ensure performance targets are met. Post-silicon VF/noise correlation to provide feedback to chip/board design teams.

Working in the Perf-Power-Binning (PPB) bring-up team at the Silicon Solutions Group in Santa Clara, CA, and have the following responsibilities: 1) Develop methodologies to characterize pre-production Silicon and understand behavior across process, voltage, and temperature (PVT) to extract maximum chip performance across workloads. Validate system-level features on Silicon through firmware testing. 2) Correlate system-level functional frequency data with in-silicon monitors (ISM) to study the frequency distribution and calculate frequency margins to compensate for device degradation over chip lifetime. 3) Calculate reliability margins for device failure mechanisms like HCI, BTI, and TDDB using foundry spice models to predict Silicon performance and degradation over chip lifetime, detect early-life failures, and calculate specs for production-level SLT screening and HTOL experiments. 4) Generate SKU specifications for SoC and GPU chips for various market segments and manage product overdrive assessment docs.

Working in the Design Enablement team developing EMIR analysis tech files for Process Design Kits (PDKs). Develop automation to generate EMIR-Totem GDSII mapping tech files. This automation will help other developers to create GDSII tech files for all GF supported PDKs. Tested the script for resistor test cases in 22FDX and via test cases in 12LP+ platforms and deployed.

Working with Foundry Technology Operations (FTO) and performing statistical studies to ensure proper yield and reliability. Carrying out statistical analysis on the latest 7nm CPU and APU products. This included tasks like: 1) Regular yield reporting and monitoring of wafers across various test insertions in and after coming out of the fab. 2) Building voltage, frequency models to find correlations among parameters in WAT, WET that affect product performance, yield. 3) Create scripts to generate yield step up charts for products across the node to track yields across timeline and identify yield trends. 4) Create Sort (WS1/WS2) and WAT reports to highlight wafer lot performance. 5) Identifying the performance of corner lot wafers with respect to the Product/Spice targets to check if they land within the characterized Spice Window for the node platform. Developed Scripts in JSL and Python to automate several tasks required for Yield Tracking and Analysis. Developed and deployed application for extraction of Tests, spec limits from KDF Files of wafers coming out of the fab. Utilized Python, SQL, Batch Scripting to build the application.

Undergone basic training in Control Panel Wiring, General Arrangement, Control Panel Testing, and a basic understanding of PLC

Focus Areas include VLSI Circuit Design, Computer Architecture

Minors in Applied Statistics