Niall Timlin-Canning
Principal Design Engineer @ Cadence
About
ASIC designer with strong experience in DDR memory controllers, timing closure at high frequencies and on advanced nodes, and functional safety certified (ISO26262).
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Ireland
Semiconductors
Verilog, SystemVerilog, VHDL, C, Python, Perl, TCL, Static Timing Analysis, Logic Synthesis, ISO 26262, Unified Power Format (UPF), Universal Verification Methodology (UVM), FPGA prototyping, Xilinx Vivado
Experience
Principal Design Engineer
Cadence
Design & Verification Engineer
CreVinn Teoranta
QA Intern
Xperi Inc.
Galway City, Ireland
Education
University of Galway
Electronic & Computer Engineering
Niall Timlin-Canning's Contact Information
Phone
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