Navjeet Singh

ASIC Design Verification Engineer @ Google

Country

United States

City

Santa Clara

Industry

Computer Hardware

Skill

SystemC, Python (Programming Language), Universal Verification Methodology (UVM), SystemVerilog, Verilog, Shell Scripting, Digital Electronics, FPGA, C++, Python, C, Cadence Virtuoso, System on a Chip (SoC)

Experience

ASIC Design Verification Engineer

Google

2023-9 - Present · 3 yrs 1 mo

Sunnyvale, California, United States

Working on TPU verification

ASIC Verification Engineer

Juniper Networks

2019-8 - 2023-9 · 4 yrs 2 mos

San Francisco Bay Area

• Architect and Develop block-level verification environments using SystemVerilog and UVM methodology. • Created performance optimized high level C++ models for ASIC used for driver development by software developers. • Developed SystemC reference models for block-level verification environments. • Write assertion based checkers to unmask protocol violations. • Develop Perl and Python scripts to improve current verification infrastructure/methodology.

Design Engineer Intern

Micron Technology

2019-1 - 2019-5 · 5 mos

San Francisco Bay Area

* Worked as Digital Design Engineer intern in 3D NAND Non-Volatile Memory(NVM) group. * Developed the framework and covergroups based on design specifications to determine functional coverage in a team of four people.