Naveena P.

Scientific Reports - VLSI Seconductor Domain Research / Journals publications - Reviwer

INTEGRATION - VLSI Research paper / publications / Journals Reviwer

IEEE - VLSI Research paper / publications / Journals Reviwer

1. A Scalable Architecture to Accelerate Digital Circuit Simulation project. Working on "Swift" (Simulation accelerator with multi-FPGA technology) project under the leadership of Prof. Daniel Sanchez, @ Massachusetts Institute of Technology 2. "High-Throughput Monitors for Pre- and Post-Silicon Verification project" under the leadership of Prof. Kevin Skadrom, @ University of Virginia, Charlottesville. 3. "Hardware Software Co-design for Graph Machine Learning on Heterogeneous Architectures" under the leadership of Prof. Viktor K. Prasanna, @ University of Southern California. 4. JUMP 2.0 Programs reviwer

• Serving as the pre-silicon emulation architect for high-complexity server platforms, including the Xion series. • Serving and Leading pre-silicon validation efforts for next-generation Intel Xeon server processors, such as Sapphire Rapids, Sapphire Rapids with High Bandwidth Memory (HBM), Granite Rapids, Sierra Forest, Diamond Rapids, Newport, and advanced artificial intelligence chips like Spring Crest, River Crest. • Working on both pre-silicon emulation and post-silicon end-to-end validation, with leadership roles across multiple functional domains and Design for Debug (DFD) domains • Responsible for emulation model bring-up and debugging activities to ensure robust platform validation. • Driving high-demand proof-of-concept projects within the emulation domain to evaluate and demonstrate new technologies. • Contributed to Intel-federal server-class CPU programs, including work on Icelake (ICX), MGR, and U.S. federal initiatives requiring high-bandwidth memory and complex server architectures. Notably, supported the U.S. Aurora supercomputer at Argonne National Laboratory, which leverages Intel’s Sapphire Rapids processors with HBM to deliver exceptional data throughput and accelerate AI and high-performance computing workloads, enabling groundbreaking scientific research and federal applications at exascale levels.

Served as a customer-facing application engineer, supporting ZeBu emulators and acting as a validation specialist for complex graphics, server, and computing chips. Held a global leadership role, directly supporting the bring-up of 15 customer designs across the US, Mexico, India, Israel, and Taiwan. Ported designs from small to large scale, targeting ZeBu emulators from single-board to 50-board configurations, with sizes from millions to billions of gates. Supported GPU/CPU-based SoC bring-up, including Linux/Android OS, BIOS, network switches, memory controllers, desktop, and server chips. Deployed and maintained transactor-based solutions (SATA, AMBA AXI, APB, UAPI, JTAG, eMMC) and have strong expertise in ZeBu transactors (zcei, zemi3), including integration, runtime, and debugging. Supported custom transactors in SystemVerilog and DPI-based proprietary interfaces. Managed model build, runtime debugging, hardware failure analysis, OS/BIOS validation, and application validation. Assessed customer requirements, selected ZeBu platforms, ported designs, validated, and optimized compile time and performance. Reproduced customer issues in-house, worked with R&D to resolve tool problems, and minimized production downtime. Recruited, trained, and developed a team of application engineers for ZeBu. Led product benchmarking, worked with R&D to meet quality requirements, reported and validated bugs, and participated in hardware/software pre-release validation. Supported all emulation phases, including parsing, elaboration, synthesis, zTopBuild, partitioning, zCoreBuild, FPGA compilation, and runtime troubleshooting. Collaborated with Synopsys sales on product demos, evaluations, and benchmarking. Authored three application notes and trained over 100 engineers in ZeBu emulation. Developed unique transactor solutions for multiple platforms.

Client: Silicon Image – QUIVER (DSP-Based Baseband SoC) • Conducted functional verification of DSP-based baseband SoC, focusing on the transmitter module. Responsibilities include creating comprehensive test plans and developing the test bench environment. Client: Intel – DS4 and DS5 • Performed verification activities for DSP-based SoCs. • Led functional verification of the MIPI protocol, developing the test bench environment from the ground up using SystemVerilog and the UVM methodology. • Integrated MBIST logic into the SoC, validated the complete SoC, and generated test patterns. • Generated ATPG patterns for USB and other modules. • Executed gate-level bring-up, unit delay simulations, and SDF-based validation.

Client: Qualcomm – Gimli and Thorin • Served as a verification engineer responsible for full-chip SoC verification. • Performed gate-level simulation (GLS) brings up, executing full-chip zero-delay and SDF-based tests. • Verified and validated modules include PLL, ARM, QDSP, reset block, ADC, and DAC. Client: DRDO (Government Organization) – Radio Manager • Acted as design and verification lead for full-chip SoC development. • Utilized AMBA Designer to create the AMBA bus matrix, integrating all modules according to SoC specifications. • Ported SystemVerilog and VMM-based test environments. • Adapted and executed subsystem and system-level tests written in Verilog, Vera, C, and assembly. • Developed test plans, test matrices, and ensured code and functional coverage to meet verification goals. • Worked on the design and verification of modules such as PLL, DMA, bus matrix, reset module, SPI, UART, and ARM11 core.

Client: Texas Instruments (Projects: Corozon, Phenix, DebugSS for Attila and Netra) • Served as the verification lead for DSP-based System-on-Chip (SoC) projects. • Adapted and integrated custom verification environments and ported all module-level and chip-level tests written in Perl, C, C++, and assembly. • Developed test plans, test matrices, and created test cases to achieve comprehensive functional coverage and meet verification goals. • Performed gate-level simulation (GLS) brings up, executing full-chip zero-delay and SDF-based tests. • Verified and validated key modules including DSP core, PLL, USB, DMA, DDR, VBUS, clock/reset blocks, and trace modules. Client: Japan-Based Telecom Company • Conducted debug subsystem verification, including test plan creation and test case development using Specman e, targeting ARM and DSP-based complex SoCs. Client: Government Organization (Radio Manager) • Served as architect for a Software Defined Radio SoC, generating feasibility study reports to support TETRA, GSM, and CDMA communication standards.

Client: Texas Instruments – OMAP, Davinci, Locasto, Xena, Puma, Attila, Netra • Served as verification lead for full-chip ARM7/9/11 and DSP-based multi-core SoCs. • Developed and integrated verification environments, porting Perl, C, C++, and assembly tests at both subsystem and system levels to achieve coverage objectives. • I worked as architect for debug subsystems and debug tools. • Performed gate-level simulation (GLS) brings up, executing full-chip zero-delay and SDF-based tests. • Led verification planning, including test plan creation, test case development, coverage analysis, and debugging of functional failures. • Utilized emulation platforms such as QuickTurn (Palladium) and ZeBu hardware for over 20 ARM and DSP-based chip designs. • Verified ARM and DSP subsystems, ICE Crusher, ICE Maker, VBUS, power and clock reset modules, timers, DDR, L1 and L2 cache modules, analog modules, and debug subsystems. • Validated system-level debug features such as stop, step, run, restore, and cache memory operations (L1, L2, I-cache, D-cache), as well as system-level reset and clock-related features. • Verified ARM and DSP processor debug features at both system and subsystem levels. • Participated in numerous design reviews, code reviews, and product specification reviews. • Served as worldwide application engineering lead for MSP430, analog products, and power management solutions. Client: Cisco • Worked on high-speed board design and simulation for Cisco network cards.

BE in Instrumentation and electronics from Bangalore University, India with First Class and distinction.

MS in Microelectronics from Birla Institute of Technology, Pilani, India with First Class.