narsimha kodur
engineering manager
About
Over 8 years of experience in ASIC Physical design implementation, verification & sign-off analysis at 65/45/32/28/20 nm process technologies. Experience in using Synopsys ICC, Cadence Encounter, Magma Talus, Mentor Olympus, along with all sign off tools.
india
hyderābād
semiconductors
physical design, vlsi, asic, physical verification, timing closure, floorplanning, static timing analysis, low power design, eda, formal verification, rtl coding, soc, dft, systemverilog, primetime, rtl design, functional verification, clock tree synthesis, tcl, lvs, cadence, logic synthesis, magma, verilog, drc, cmos, debugging, logic design, icc, ic, cadence virtuoso, integrated circuit design, fpga, modelsim, processors, analog circuit design, very large scale integration, application specific integrated circuits, system on a chip
Experience
applicaiton consultant for asic physical design products
synopsys
Was working as Consultant to SAMSUNG South Korea, on ASIC Physical design.
engineering manager
intel corporation
asic physical design engineer
amd r&d center hyderabad
Worked as ASIC Physical Design Engineer at AMD R&D center, Hyderabad, in Digital TV division (Now it’s part of Broadcom)
lead design engineer
texas instruments
Physical Design engineer for Embedded Connectivity, Embedded Processor products - Full chip & Sub-chip level implementation & Sign-off
pd application engineer
synopsys
Worked as application engineer for Physical design products at Synopsys India
senior staff ic design engineer
broadcom
narsimha kodur's Contact Information
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