Nagaraju Munigala

Physical Design Engineer with 13+ years of deep technical ownership and expertise across cutting‑edge nodes from 20nm to 2nm (TSMC). Specialized in driving subsystem and block-level implementation, including PnR, STA, physical verification, EMIR, and signoff execution. Delivered 20+ successful tapeouts of high‑complexity, multi‑million‑gate designs across CPU, GPU and SoC subsystems.Recognized for leading PPA strategy, architecting floorplans, optimizing clock/power distribution, and resolving advanced-node challenges such as IR‑drop, EM reliability, variation impacts, and routing bottlenecks. Skilled in guiding cross-functional teams, mentoring junior engineers, and establishing scalable flows for PnR, timing closure, ECO convergence, and signoff quality.