brian myrick

electrical engineer ii

About

Principal Hardware Engineer with extensive FPGA and board design experience. Familiar with all aspects of the design process from requirements to development, test, and integration. Proven track record of delivering complex products on time and within budget. Core Competencies Writing detailed specifications In-depth knowledge of the Xilinx, Altera, and Lattice tool suites Verilog and VHDL coding Simulation Design Verification Synthesis Static Timing Analysis Perl scripting Python scripting Linux scripting FPGA bring up In-depth knowledge of the Cadence Allegro tool suite Specifying components Circuit design Schematic capture PCB design with constraints Board layout Hardware validation Lab debug Signal Integrity Knowledgeable in the use of oscilloscopes and logic analyzers

Country

united states

City

boston

Industry

computer networking

Skill

fpga, asic, verilog, vhdl, verification, synthesis, timing analysis, debugging, xilinx, altera, lattice, perl, xilinx ise, altera quartus, lattice diamond, embedded systems, telecommunications, ethernet, pcie, amba ahb, cadence, synopsys, schematic capture

Experience

senior electrical engineer

raytheon

2015-4 - Present · 11 yrs 6 mos

hardware engineer

cisco

2009-1 - 2014-10 · 5 yrs 10 mos

consulting engineer

mayflower communications

2005-7 - 2005-12 · 6 mos

Designed an AMBA AHB interface and a general purpose External Bus Interface.

consulting engineer

sentech

2005-1 - 2005-6 · 6 mos

Designed an FPGA with an embedded processor, an SRAM controller, a visible camera controller, an IR camera controller, and an azimuth controller.

consulting engineer

teradyne

2004-1 - 2004-12 · 1 yr

Designed a high speed DDR SRAM interface that allowed the automatic waveform generator (AWG) card to meet the 6GHz performance goal. Performed post-layout timing analysis using Quartus II. Designed the programming interface for the AWG FPGA. Involved making trade-offs between hardware and software complexity. Verified the AWG and LFN FPGA’s using VCS and Debussy. Involved debugging verilog and C++ code.

principal hardware engineer

appian communications

2000-1 - 2003-12 · 4 yrs

Designed and debugged the packet classification and packet scheduling FPGAs for an Ethernet to Sonet/SDH multi-service switch. Developed algorithms for packet scheduling. Required knowledge of various packet scheduling concepts including, but not limited to guaranteed v. best effort scheduling, priority scheduling, WFQ, token buckets and differentiated services (QOS). Developed algorithms and data structures for packet classification. Required knowledge of the services being offered by the product, network protocols and packet formats, including Ethernet, Frame Relay, PPP, MPLS, VLANs. Involved analysis of performance and scalability of various architectures.

electrical engineer ii

raytheon ids

2015-4 - Present · 11 yrs 6 mos

principal hardware engineer

crossbeam systems

2006-1 - 2008-12 · 3 yrs

Designed and debugged the transmit path between an 8 lane PCIE interface and 4 FOCUS bus connections using Synplicity/Synplify, Altera Quartus, Stratix II EP2SGX90. Designed and debugged a content scanner (CSF) FPGA using Synplicity/Synplify, Altera Quartus, Stratix II EP2S130. The CSF FPGA included a 200MHz DDR2 SDRAM interface, and a 200MHz ZBT SRAM interface.