Muthukumaran Vaithianathan

Senior Staff Engineer @ Samsung Electronics America

About

Muthukumaran Vaithianathan is a Lead Chip Architect and Silicon Technologist. Has a demonstrated history of working in Consumer Electronics Industry. Skilled in ASIC/FPGA complete chip development cycle such as 1. Silicon RTL Design 2. Mixed-Signal (DMS) and pure Digital (DIG) SV-TB in a UVM framework. 3. Board level Validation. Prolific FPGA Writer and FPGA Expert. Commercial Product worked in: o Samsung : Cellular Network Mobile Handsets (UE) and Wearables. Google: Pixel Mobile Handsets o Nokia : Mobile Handsets (UE) and BaseStation (NodeB). o NXP : USB2.0 pen drive storage devices. USB3.0 Type-C PD (Power delivery) chip o Spirent Technologies : 4G/LTE Modem for Commercial Base station (NodeB) and Mobile Handset(UE) form factor for Cellular Network Emulator . o TruePosition Inc. : E911-LMU (Location Measurement Unit) 3G/4G/LTE Modem design. My bibliometrics and author profiles: o Scopus Author ID : 59139439400 o ORCID ID : https://orcid.org/0000-0002-9779-1608 o Google Scholar ID : Yh0xzNYAAAAJ&hl o ResearchGate ID : https://www.researchgate.net/profile/Muthukumaran-Vaithianathan-3 o 10 IEEE Xplore Digital Library publications o 30+ Publications with 525+ citations in Google Scholar and 600+ citations in ResearchGate

Country

United States

City

San Diego

Industry

Consumer Electronics

Skill

ClearCase, Embedded Systems, Debugging, C, Verilog, FPGA, ARM, Perl, LTE, VHDL, GSM, ASIC, RTOS, Digital Signal Processors, TCL, Embedded Software, Ethernet, ModelSim, SoC, Field-Programmable Gate Arrays (FPGA)

Experience

Senior Staff Engineer

Samsung Electronics America

2018-6 - Present · 8 yrs 4 mos

San Diego, California

Contributing for the research and development of mixed-signal IC design DMS, and standalone Digital SV-TB UVM verification activities for 5G/mmWave/NTN RFIC (FR1, FR2), GNSS, and FMCW Radar. Have modelled analog components such as, Op-Amp, TIA, LPF & HPF for ABB (Analog baseband) in SVRNM for FMCW Radar DMS Verification. Created UVM DMS Verification environment from scratch. On RTL design side, contributing for PCIe, CXL & UCIe RTL development activities.

BCS Fellow

BCS, The Chartered Institute for IT

2024-12 - Present · 1 yr 10 mos

Sigma Xi Full Member

Sigma Xi, The Scientific Research Honor Society

2024-3 - Present · 2 yrs 7 mos

SMIEEE

IEEE

2022-11 - Present · 3 yrs 11 mos

ASIC/FPGA Verification Engineer

Qualcomm

2017-11 - 2018-6 · 8 mos

San Deigo CA USA

Contributed for numerous direct test-sequence for the for the research and development of evolving Low Power & Legacy Classic Bluetooth specification. Contributed in formulating Formal property verification with SVA for the IP. Added assertions for the interface & BLE+BTC functional Packet processing. Worked as Consultant.

ASIC/FPGA Design Verification & Validation Engineer

Cisco

2016-4 - 2017-10 · 1 yr 7 mos

San Francisco Bay Area

Responsible for creating Verification plan and develop TB for Switch Router board's for 6 different projects. Acted in 3 different Roles. Design-Verification Role: Created Class based SV-TB and UVM-TB flavors both. Developed standalone SV-TB environment [from scratch] initially and migrated that to UVM methodology later. Reproduced many field level [real time] validation bugs, in the UVM TB environment and root-caused the issue. RTL design: Wrote RTL design, by migrating and integrating the legacy RTL to the new platform with innovative features Board-level Validation: Validating RTL in the board. Wrote validating python scripts. Worked as Consultant.

ASIC/FPGA Design Verification & Validation Engineer

Intel Corporation

2015-9 - 2016-3 · 7 mos

Hillsboro OR

Was involved in development of DDR-4/T UVM Verification and Validation from scratch. Wrote assertions and coverage for the same. Worked as Consultant.

ASIC/FPGA Design Verification & Validation Engineer

NXP Semiconductors

2014-6 - 2015-8 · 1 yr 3 mos

San Francisco Bay Area

Responsible for ASIC Verification. Write Test plan. Create UVM verification environment for USB 3.0 Type-C from scratch to metal. Wrote Scoreboard, Sequences, Assertions & Coverage. Worked as Consultant.

Technical Lead

Altran

2009-2 - 2014-6 · 5 yrs 5 mos

Chennai, Tamil Nadu, India

Responsible for ASIC/FPGA Design, Verification & Validation for 3G/LTE PHY development and IP development.

Technical Lead

Nokia

2008-2 - 2009-1 · 1 yr

Dallas/Fort Worth Area

Responsible for Design, Verification & Validation of PHY/L1 layer for 3G in FPGA. This Modem is for Location Measurement Unit(LMU) crucial for E911(Enhanced 911) emergency service application. Contributed as Consultant.