Mukundan Swaminathan

Senior Technical Director & Lead GPU/ML Core IP @ Intel

About

Hands-on Lead Managing next-gen GPU/ML Compute Vector & Tensor Core IP development Previous experience in leading development and production of low power machine learning HW accelerators for audio and speech understanding applications, designing critical hardware components in a System On Chip like DRAM controller, Clock, and Reset unit. Established, lead, and trained Full Chip Integration, Model release methodology for SOC supporting a team of 200 engineers cross-site.

Country

United States

City

Mountain View

Industry

Semiconductors

Skill

GPGPU, Graphics Processing Unit, FPGA, VLSI, SoC, Debugging, Logic Design, Emulation, Hardware, RTL design, SystemVerilog, Verilog, ASIC, Semiconductors, System on a Chip (SoC), IC, RTL Design, Very-Large-Scale Integration (VLSI), Processors, VHDL

Experience

Senior Technical Director & Lead GPU/ML Core IP

Intel

2021-1 - Present · 5 yrs 9 mos

Santa Clara, California, United States

Leading the development of next-generation GPU and ML Core IP for accelerating ever-evolving 3D, Media, Compute, and ML workloads.

Sr. Manager/Tech Lead HW acceleration

Intel

2016-1 - 2021-1 · 5 yrs 1 mo

San Francisco Bay Area

Lead from the definition, development to production of ML/AI Accelerator for Low Power inferencing use cases.

Research Engineer

Intel Labs

2013-6 - 2015-12 · 2 yrs 7 mos

San Francisco Bay Area

2014: Micro-Architecture Research Lab, Intel Labs 2013: Leading and driving the FW/Driver/SW bring-up effort for the image capturing unit of the Camera subsystem

Sr. Component Design Engineer

Intel

2012-3 - 2013-6 · 1 yr 4 mos

Santa Clara

Designing DRAM controller for tablet based SOC. Co-developing & designing Clock and Reset unit for a tablet based SOC. Consulted on Full Chip integration methodologies and flow for 14nm SOC product and supported around 200 engineers cross site.

Component Design Engineer

Intel

2008-9 - 2012-3 · 3 yrs 7 mos

Santa Clara

Full Chip integration lead for a 32nm DHG SOC products. Lead & established Full Chip Integration, Model release flow and methodology for a complete SOC and supported around 200 engineers cross site. Analyzed Performance and Bandwidth for DRAM Memory Controller for Atom based Consumer Electronics SOC. Implemented proto typed for QoS (Quality Of Service) arbitration policies for both performance and bandwidth improvements for the same DDR Memory Controller. Designed DMA Controller compatible for SOC memory interface for High Definition Video capture unit for Atom based SOC Implemented post silicon debug feature, VISA (Visualization Of Internal Structure Architecture) for the Atom based Consumer Electronics SOC.