Mohsin Ali

Technical Lead Manager (GPU Verification) @ Intel

About

ASIC Verification Engineer with significant experience spanning over multiple line of products ranging from SoC, Network Processor, Communications, CPU, Bus Bridges, and Chipsets. Skilled in verification methodologies, strategy, testbench architecture, BFM, Checker/Monitor, test plan development, functional coverage, and gate level simulations. Worked as individual contributor and team lead/manager in local onsite to multi-site projects. Strong understanding of SoC verification methodologies and reusable Verification IP requirements.

Country

United States

City

Santa Clara

Industry

Computer Hardware

Skill

Universal Verification Methodology (UVM), SystemVerilog, SoC, ASIC, Debugging, Semiconductors, Simulations, VLSI, Verilog, High Performance Computing (HPC), Functional Verification, Processors, RTL Design, PCIe

Experience

Technical Lead Manager (GPU Verification)

Intel

2021-1 - Present · 5 yrs 9 mos

San Jose, California, United States

Leading and contributing to the development of Emulation compatible Bus Functional Models (BFM) for Power Management flows.

SOC Technical Lead/Manager (ALTERA)

Intel

2016-3 - 2020-12 · 4 yrs 10 mos

San Jose, California, United States

Intel-PSG (Altera) Corp: Verification Technical Lead for Ethernet Transceiver ASICs (a.k.a.Tiles) of the FPGA Stratix and Agilex product lines. Leading a team of 10 members (including offshore contractors).

Principal Verification Engineer

Oracle

2014-4 - 2016-1 · 1 yr 10 mos

San Francisco Bay Area, Santa Clara, CA

Verification of the Coherency and RAS features of the next generation M series multi-core SPARC processors.

Architectural Verification Technical Lead/Manager

Intel

2012-1 - 2014-3 · 2 yrs 3 mos

Santa Clara, CA, USA

Full Chip (FC) Verification technical Lead/Manager for the next generation Xeon Phi chip, a multi-core MIC (Many Integrated Cores) chip targeted for High Performance Computing. Technical Lead for a team of engineers across 3 sites (one international site). Involved in creation of the FC test plan and strategy, test writing, simulations debugging, development of checkers, monitors, BFMs. Coordinated overall verification activities across different cluster verification groups making up the FC model. Tasks included communicating management’s expectations and directions, tracking test plans, functional coverage plans and test environment development readiness, as well as tracking the teams’ execution progress

Senior Verification Engineer

Intel

2002-1 - 2011-12 · 10 yrs

Hudson, MA, USA

Full Chip front-end Integration Lead of next generation PCH Chipset (South Bridge) Lynx-Point, an SoC based product. Coordinated and executed the RTL and Test Environment components integration into Full Chip model across three sites (CA, MA and Penang/Malaysia). Also responsible for managing and integrating a set of Soft IP into the model build flows. Responsible for PCI block, Communication cluster and then Full Chip verification of Intel’s first IA core (Pentium) based SoC Network processorNetwork Processor. Gate Level Simulation Lead: Coordinated and executed the gate level simulation activities between different clusters, and backend team members. Debugged GLS model build issues and simulation failures. Invovled in defining verification methodologies, strategies, and deveploment of test plans, BFMs, checker, monitors, both contrained random and genetic algorithm based stimulus generation, functional coverage, tools and IP evaluation from vendors.