Marimuthu Kumar Murugan
Engineering Manager @ Intel
About
20 years of experience in VLSI front end design and verification. ASIC and FPGA design. SOC design and verification with embedded processors. RTL design, Synthesis, Simulation,formal verification, Spyglass. On-chip bus protocol designs: AHB, OCP, PLB and OPB. Low power design, GPU, USB sub-chip design, ONFI, SSD NAND Flash controller Design Patents: Configuration Communication template for hardware co-processors (US Patent) Papers: Published papers on USB, Low power techniques in TIITC
United States
San Francisco Bay Area
Semiconductors
Verilog, System Design, RTOS, VLSI, ARM, ASIC, SoC, Semiconductors, Device Drivers, FPGA, Digital Signal Processors, Hardware Architecture, Functional Verification, Debugging, EDA, Perl, Microprocessors, VHDL, Hardware, Embedded Software
Experience
Engineering Manager
Intel
San Jose, California, United States
Storage SOC Design Architect
Samsung Electronics
San Francisco Bay Area
Principal Engineer - Non-volatile Engineering Group
Micron Technology
San Francisco Bay Area
SSD Controller Design
Senior IP logic design engineer - Mixed Signal IP Group
Intel
San Francisco Bay Area
High Speed IO Design, SERDES design, Lint, Low power using UPF
Senior ASIC Design Engineer - Advanced Controller Group (SSD)
Micron Technology
San Jose
Responsible for the SSD NAND flash interface controller and arbiter design. - Micro Architecture of the sub modules - RTL Verilog Design - Block Level Verification - Verification Requirement document - Spyglass Lint checking, CDC, synthesis, timing constraint.
Technical Manager - Engineering & RnD Services
HCLTech
ASIC and FPGA Design and verification Lead, Embedded design, Program Management, Freshers campus hiring , Internship and Training programs, technical project proposals, onsite and offshore customer engagement.
Senior Design Engineer - Wireless Design Group
Texas Instruments
OMAP 3430, 4430 and 5430 Subchip design of multimedia IPS like USB 2.0, USB OTG, GPU SGX530 and 540 which includes micro architecture, detailed design document, integration document, RTL VERILOG coding, simulation, synthesis, LEC, spyglass lint and CDC clock domain crossing, scripting, ECOs. 65, 45 and 28 NM design,. ASIC front end development/verification .
Senior Member Technical Staff
Poseidon Design Systems
Micro Architecture, Design Specification, RTL VHDL and Verilog Coding. FPGA SOC designs, Front-end RTL design and verification. Hardware and Software partitioning. C to RTL HW accelerator implementation.. Design of hardware accelerators.
Member Technical Staff
HCLTech
DSP Filters and AMBA AHB IP Design and Verification.
Education
The Wharton School
Business Administration and Management, General
Harvard Business School
Stanford University
Artificial Intelligence, machine learning , cloud computing
Fall 2018-2019
Sri Ramakrishna Engineering College
Electronics and Communication
Student - Engineering
Marimuthu Kumar Murugan's Contact Information
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