Mike Candelario
Senior Package Layout Engineer @ NVIDIA
-
Taiwan
Semiconductors
Computer-Aided Design (CAD), 3D Computer Aided Design (3D CAD), Project Management, Design Rule Checking (DRC), Design for Manufacturing, Research and Development (R&D), ZWCAD, Cadence APD, Allegro Package Designer, AutoCAD, SolidWorks, Integrated Circuits (IC), PCB Design, Autodesk Inventor, CAM350, Zuken PWS, Geometric Dimensioning & Tolerancing, Failure Mode and Effects Analysis (FMEA), MEMS
Experience
Senior Package Layout Engineer
NVIDIA
Senior IC Packaging Engineer
iCana
New Taipei City
R&D Design Engineer
UTAC
Bangkok Metropolitan Area, Thailand
IC Package Design Engineer
Amkor Technology, Inc.
Laguna Technopark, Binan Laguna, Philippines, 4024
PCB Design Engineer
KYOCERA Global
Libis, Quezon City, Philippines, 1110
Education
Polytechnic University of the Philippines
Electronics and Communications Engineering
Mike Candelario's Contact Information
Phone
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