Mehul Patel

MBIST Verification - MBIST Pattern re-targeting using iJTAG (IEEE - 1687) - MBIST verification at IP level - MBIST Tester Pattern Delivery For complete IP - Actively involved in Silicon bring up for MBIST vectors - Working knowledge of ICL/PDL (iJTAG IEEE 1687)

Supporting Synopsys DFT Solutions world wide (Onsite/Offsite)  Scan Insertion: DFT Compiler  Scan Compression: DFTMAX, DFTMAX Ultra  ATPG: TetraMAX  SpyGlass DFT

Worked as DFT engineer - Scan Chain Insertion using RTL Compiler of Cadence - Scan Compression and power aware scan insertion - Pattern generation using Encounter Test of Cadence - MBIST using Tessent of Mentor - JTAG - Boundary Scan insertion and simulation using Tessent of Mentor

Worked on - Block level scan stitching in Hierarchical DFT architecture. - EDT insertion using TestKompress - Pattern generation using TestKompress (Mentor ATPG tool) - Pattern simulation (timing and no-timing) using VCS - Boundary scan simulation - Analog loopback test of SerDes BIST using JTAG. - PLL frequency lock test using JTAG. - DRO (Debug Ring Oscillator) testing using JTAG - IOMUX verification - OCC verification

Worked with DFT Team in Automotive Product Group at STMicroelectronics. Having experience of - Scan chain insertion using DFT compiler - Pattern generation using TMAX - Test Mode Entry pattern debugging - Assertion Based Verification using Incisive Formal Verifier tool for IOPADs and DFT like BIST connectivity etc.. - Functional verification of Multi Timer Unit (IP). - Perl Scripting to generate pmap file from xml file and generate assertion for formal verification Also having basic knowledge of DFT concept like - Automatic Test Pattern Generation (ATPG) - MBIST Flow - JTAG - Boundary Scan - Scan Design - Fault Models Tools known: - DFT Compiler and TetraMAX of Synopsys - NCSim, RTL Compiler and Incisive Formal Verifier of Cadence Scripting Languages: - Good working knowledge of Perl - Tcl