Meera Ramprasad

Meera Ramprasad

Senior Design Engineer @ Infineon Technologies

About

Hello there! I'm a recent MS EE (Integrated Circuits & Systems) graduate from Columbia University. I'm broadly interested in the Analog & Mixed Signal Design space. During Summer 2024, I worked as an Intern in the Millimeter Wave Radar team at Texas Instruments designing Oscillators and Slicers for Analog Phase Locked Loops in FMCW Radar Products. Before my MS, I was a part of the Input-Output (IO) Library Design team at Infineon Technologies, India, where I worked on various stages in the Analog Design flow, including design, layout, verification, and back-end view generation. Over the course of my MS and work experiences, I've been a part of two successful tape-outs and numerous projects in the Analog, Mixed Signal, and RF Design domains. I graduated from BITS Pilani, India in 2022. Through my experiences, I've built a strong foundation in core electronics concepts, which I've harnessed to identify root-cause issues in design and develop a systematic approach to solving problems. I'd love to connect to explore more opportunities and discuss shared interests. Please feel free to reach out to me.

Country

-

City

United States

Industry

Semiconductors

Skill

JMP, Failure Analysis, Module Development, Systems Design, Optical Sensors, Phase-Locked Loop (PLL), Floorplanning, Behavioral Modeling, RF Design, Radio Frequency (RF) Engineering, Cadence Virtuoso Layout Editor, Transmission Lines, Impedance Matching, Mixed-Signal IC Design, Analog Integrated Circuit Design, Semiconductor Physics, Semiconductor Engineering, EDA, Logic Design, Amplifiers

Experience

Infineon Technologies

Senior Design Engineer

Infineon Technologies

LinkedIn
2025-10 - Present · 1 yr
Apple

Design Engineer

Apple

LinkedIn
2025-2 - 2025-9 · 8 mos

Cupertino, California, United States

Health Sensing Hardware Team • Developed module & system level designs for front-end sensing modules used in heart-rate measurement products. • Created Designs of Experiment (DOEs) to enable system verification for analog signal chains and utilized statistical process control to evaluate product yield. • Conducted failure analysis (FA) deep dives and generated detailed corrective-action proposals in liaison with cross function team members.

Columbia University

Course Assistant

Columbia University

LinkedIn
2024-9 - 2024-12 · 4 mos

New York City Metropolitan Area

ELEN E4312 - Analog Electronic Circuits under Prof. Peter Kinget • Graded student homeworks and term examinations in Analog Electronic Circuits for a class of 90+ upper undergraduate and graduate students. • Conducted weekly office hours and doubt-clearing sessions for circuit theory lessons and circuit simulation tutorials. • Evaluated course projects involving design and simulation of Two-Stage Miller Amplifiers.

Texas Instruments

Analog IC Design Intern

Texas Instruments

LinkedIn
2024-5 - 2024-8 · 4 mos

Dallas, Texas, United States

FMCW Radar Team - Clocking & PLLs • Designed a crystal oscillator and slicer to generate 50 MHz clock signals for analog phase-locked loops (APLLs) in millimeter-wave Automotive Radar products on a 28nm technology node using Cadence Virtuoso. • Optimized circuit components for PVT invariance, improved the phase noise performance while maintaining a total current consumption of 2 milli-amperes and a startup time under 700 microseconds. • Created behavioral models for the functional verification of test and operating conditions of the Oscillator in Verilog-AMS.

Infineon Technologies

Design Engineer

Infineon Technologies

LinkedIn
2022-7 - 2023-7 · 1 yr 1 mo

Bangalore Urban, Karnataka, India

IO Team • Designed Input Output (IO) circuit libraries for GPIO & MIPI interface standards, including 40V high-voltage tolerant & Silicon-On-Insulator (SOI) based IO Pads for Automotive & RF Front-end applications. • Created test benches, performed pre- and post-silicon verification for IO Pads and test chips, yield analysis & reliability testing. • Formulated validation plan templates for GUI-based automation of three critical functions - extraction of validation data, library characterization and back-end view generation for Computer-Aided-Design (CAD) Tools. • Collaborated with design team members and customers for design reviews, automation projects and IO library releases.

Infineon Technologies

Intern

Infineon Technologies

LinkedIn
2022-1 - 2022-6 · 6 mos

Bangalore Urban, Karnataka, India

• Developed a 40V high-voltage tolerant receiver buffer on Cadence Virtuoso for GPIO interfaces. • Generated layouts for logic blocks in the receiver, conducted layout checks and extracted parasitic data for post-layout verification.

USC Viterbi School of Engineering

Research Intern

USC Viterbi School of Engineering

LinkedIn
2021-8 - 2021-12 · 5 mos

• Designed Analog Neuromorphic Circuits to mimic the spiking behaviour of neural components with the TSMC 180 nm Process Design Kit (PDK). • Modelled neural navigation and dynamic changes in neural paths using spike-sensing Python scripts for controlling SPICE simulations.

International Institute of Information Technology Hyderabad (IIITH)

Research Intern

International Institute of Information Technology Hyderabad (IIITH)

LinkedIn
2021-5 - 2021-7 · 3 mos

Hyderabad, Telangana, India

• Modelled an electrically small surface mount inductor as an antenna on CST Microwave Studio for oscillators in full-custom transceiver ICs for medical devices operating in 400-406 MHz Medical Radiocommunications Frequency Band. • Formulated antenna's field equations, radiation zone boundaries and path loss models and accomplished transmission up to 10 feet.

National University of Singapore

Intern

National University of Singapore

LinkedIn
2019-12 - 2020-1 · 2 mos

Singapore

• Devised a wearable health monitoring system with a heart-rate sensor, accelerometer and step counter to reduce healthcare costs for users by 40%, built a working prototype using a Raspberry Pi and an ARM-based microcontroller. • Implemented a Deep Learning-based Pose-Correction Model with a 3-D Camera to identify real-time errors in exercise regimens and presented prototype results to a 4-member panel.

Education

Columbia University

Columbia University

LinkedIn

Electrical and Electronics Engineering

2023-8 - 2024-12 · 1 yr 5 mos

Specialization in Integrated Circuits and Systems; focus in Analog & Mixed Signal IC Design

Birla Institute of Technology and Science, Pilani

Birla Institute of Technology and Science, Pilani

LinkedIn

Electronics and Communications Engineering

2017-8 - 2022-7 · 5 yrs
Birla Institute of Technology and Science, Pilani

Birla Institute of Technology and Science, Pilani

LinkedIn

Mathematics

2017-8 - 2022-7 · 5 yrs

Meera Ramprasad's Contact Information

Email

******@***.com

Phone

(**) *** ****

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