Meera Ramprasad
Senior Design Engineer @ Infineon Technologies
About
Hello there! I'm a recent MS EE (Integrated Circuits & Systems) graduate from Columbia University. I'm broadly interested in the Analog & Mixed Signal Design space. During Summer 2024, I worked as an Intern in the Millimeter Wave Radar team at Texas Instruments designing Oscillators and Slicers for Analog Phase Locked Loops in FMCW Radar Products. Before my MS, I was a part of the Input-Output (IO) Library Design team at Infineon Technologies, India, where I worked on various stages in the Analog Design flow, including design, layout, verification, and back-end view generation. Over the course of my MS and work experiences, I've been a part of two successful tape-outs and numerous projects in the Analog, Mixed Signal, and RF Design domains. I graduated from BITS Pilani, India in 2022. Through my experiences, I've built a strong foundation in core electronics concepts, which I've harnessed to identify root-cause issues in design and develop a systematic approach to solving problems. I'd love to connect to explore more opportunities and discuss shared interests. Please feel free to reach out to me.
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United States
Semiconductors
JMP, Failure Analysis, Module Development, Systems Design, Optical Sensors, Phase-Locked Loop (PLL), Floorplanning, Behavioral Modeling, RF Design, Radio Frequency (RF) Engineering, Cadence Virtuoso Layout Editor, Transmission Lines, Impedance Matching, Mixed-Signal IC Design, Analog Integrated Circuit Design, Semiconductor Physics, Semiconductor Engineering, EDA, Logic Design, Amplifiers
Experience

Design Engineer
Cupertino, California, United States
Health Sensing Hardware Team • Developed module & system level designs for front-end sensing modules used in heart-rate measurement products. • Created Designs of Experiment (DOEs) to enable system verification for analog signal chains and utilized statistical process control to evaluate product yield. • Conducted failure analysis (FA) deep dives and generated detailed corrective-action proposals in liaison with cross function team members.

Course Assistant
New York City Metropolitan Area
ELEN E4312 - Analog Electronic Circuits under Prof. Peter Kinget • Graded student homeworks and term examinations in Analog Electronic Circuits for a class of 90+ upper undergraduate and graduate students. • Conducted weekly office hours and doubt-clearing sessions for circuit theory lessons and circuit simulation tutorials. • Evaluated course projects involving design and simulation of Two-Stage Miller Amplifiers.

Analog IC Design Intern
Dallas, Texas, United States
FMCW Radar Team - Clocking & PLLs • Designed a crystal oscillator and slicer to generate 50 MHz clock signals for analog phase-locked loops (APLLs) in millimeter-wave Automotive Radar products on a 28nm technology node using Cadence Virtuoso. • Optimized circuit components for PVT invariance, improved the phase noise performance while maintaining a total current consumption of 2 milli-amperes and a startup time under 700 microseconds. • Created behavioral models for the functional verification of test and operating conditions of the Oscillator in Verilog-AMS.

Design Engineer
Bangalore Urban, Karnataka, India
IO Team • Designed Input Output (IO) circuit libraries for GPIO & MIPI interface standards, including 40V high-voltage tolerant & Silicon-On-Insulator (SOI) based IO Pads for Automotive & RF Front-end applications. • Created test benches, performed pre- and post-silicon verification for IO Pads and test chips, yield analysis & reliability testing. • Formulated validation plan templates for GUI-based automation of three critical functions - extraction of validation data, library characterization and back-end view generation for Computer-Aided-Design (CAD) Tools. • Collaborated with design team members and customers for design reviews, automation projects and IO library releases.

Intern
Bangalore Urban, Karnataka, India
• Developed a 40V high-voltage tolerant receiver buffer on Cadence Virtuoso for GPIO interfaces. • Generated layouts for logic blocks in the receiver, conducted layout checks and extracted parasitic data for post-layout verification.

Research Intern
• Designed Analog Neuromorphic Circuits to mimic the spiking behaviour of neural components with the TSMC 180 nm Process Design Kit (PDK). • Modelled neural navigation and dynamic changes in neural paths using spike-sensing Python scripts for controlling SPICE simulations.

Research Intern
Hyderabad, Telangana, India
• Modelled an electrically small surface mount inductor as an antenna on CST Microwave Studio for oscillators in full-custom transceiver ICs for medical devices operating in 400-406 MHz Medical Radiocommunications Frequency Band. • Formulated antenna's field equations, radiation zone boundaries and path loss models and accomplished transmission up to 10 feet.

Intern
Singapore
• Devised a wearable health monitoring system with a heart-rate sensor, accelerometer and step counter to reduce healthcare costs for users by 40%, built a working prototype using a Raspberry Pi and an ARM-based microcontroller. • Implemented a Deep Learning-based Pose-Correction Model with a 3-D Camera to identify real-time errors in exercise regimens and presented prototype results to a 4-member panel.
Education
Meera Ramprasad's Contact Information
Phone
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