Muhammad Mozammal Raju

Signal and Power Integrity Analysis of Chiplet-Based Advanced Packaging Systems

• Via optimization and trace width sweeping to find optimized insertion loss, return loss and matched impedance. • Breakout trace analysis to find optimal IL, RL, NEXT, FEXT and impedance discontinuity between matched and unmatched trace length for both differential and single ended track. • S parameter extraction of DDR5 channels using PowerSI. • S parameter to eye diagram conversion simulation of DDR5 channels using Turin s2eye tool to simulate the eye height and width to check whether it passes the specs or not. • Analyze an interconnect or high-speed serial link using Serial Link Designer (SLD) based on BER and eye mask to characterize if the interconnect has the compliance to pass the spec.

• Evaluated Boards for SERDES characterization of data rate 112G/53G/25G/10.31G/10G from different technologies (7nm,12nm and 14nm), run the BER tests on boards under various environment and verified the compliance tests under different standards of IEEE802.3ck, IEEE802.23bs/cd. • Performed compliance tests TP1a for date rate of 53G/25G/10G. • Utilized cadence allegro to route high-speed traces in the boards by setting up the constraint manager. • Modeled full package Serdes channel (C4bumps to BGA) and extracted S parameter in HFSS. • Performed micro-probe measurement using Gigatest and GGB microprobes to troubleshoot the crosstalk and attenuation loss at the BGA location on the PCB. • Conducted material characterization for various test boards under different temperatures, measured S-parameters and time domains for analysis and perform de-embedding traces to eliminate unnecessary ones. • Investigate the cross-section of test card boards to find the surface roughness of Signal traces and Ground. • Utilized combinations of stack cable, breakout board, PCB, T/crosstalk couplers, crosstalk box to build channels of desired IL and ICR to characterize ASICs and SERDES. • Determined optimal trace width and pitch for microstrip and strip line impedance matching. • Used HFSS to perform electromagnetic modeling of complex three-dimensional structures to optimize SI performance of the PCB. • Performed via optimization and trace width sweeping to find optimized insertion loss, return loss and matched impedance. • Identify the routing issues on the boards such as crosstalk or signal integrity problems. • Performed DC IR drop analysis in PowerDC for different voltage rails in PCBs. • Performed AC analysis using PowerSI to find the deviation from targeted impedance. • Optimized PDN to achieve target impedance using PowerSI, OptimizePI tool.

I am researching for suitable dopants those can increase ionic conductivity, stability, electrochemical window as well as life time of solid Li electrolyte LLZO.