Mayur Kubavat
Design Verification Engineer @ Google
About
Design Verification Engineer with 10+ years of experience building and scaling verification environments for complex IP and SoC designs. Currently at Google working on TPU and PCIe verification. I specialize in developing SystemVerilog/UVM-based verification environments, formal verification flows, and assertion-based verification methodologies. My work spans constraint-random verification, coverage-driven strategies, and verification planning from Vplan development through closure. Technical focus areas: SystemVerilog, UVM, SVA, Formal Verification, PCIe, LPDDR4/5, AMBA ACE/AXI, ARM Architecture, Python.
United States
Mountain View
Computer Software
Design Verification Methodologies, UVM/SystemVerilog, Functional Verification, UVM, SystemVerilog, Computer Architecture, Assertion Based Verification, Formal Verification, ARM Architecture, System on a Chip (SoC), TPU, PCIe, Application-Specific Integrated Circuits (ASIC), C, Verilog, Unified Power Format (UPF), Microcontrollers, Digital Circuit Design, VHDL, Assembly Language
Experience
Design Verification Engineer
Sunnyvale, CA
Design Verification Engineer
Mountain View, California, United States
Design Verification Engineer
Bangalore, India
Design Verification Engineer
Analog Devices
Bangalore, India
Trainee
Maven Silicon
Bangalore
Education
Centre for Development of Advanced Computing (C-DAC)
VLSI and Embedded Systems Design
M.E. coursework at C-DAC ACTS, Pune (MeitY). Focus: ASIC/FPGA design, HDLs, and verification methodologies. Degree awarded by Gujarat Technological University.
Gujarat Technological University (GTU), Ahmedabad
VLSI and Embedded Systems Design
Mayur Kubavat's Contact Information
Phone
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