Mayank Shukla

Senior Lead Engineer @ Qualcomm

About

Senior STA engineer with more than 4 yrs of experience in timing closure of high frequency blocks at latest tech nodes down to 3nm. *Experienced in analysing the clock tree and providing pointed feedback to resolve skew, latency and clock divergence related issues. *Experienced in generating timing ECOs via PTECO, Tweaker, Prime closure and Tempus ECO. Proficient in generating manual ECOs and handshaking with PD team for their implementation. *Experienced in validating constraints and correlation of timing at block and SOC level, PD and STA level. *Proficient with both Primetime and Tempus and have handled multiple blocks with instance count ranging from 10 million to 50 Million. *Experienced in HyperScale methodology used to close hierarchical timing signoff of designs having very high instance count. *STA enthusiast looking forward to explore more in this vast domain in a challenging environment.

Country

India

City

Delhi

Industry

Wireless

Skill

Physical Design, ASIC Design, Static Timing Analysis, Synopsys Primetime, Timing Closure, Verilog, Perl, Digital Designs, Shell Scripting, TCL, Electronic Circuits, Timing, Signal Integrity, Tempus, Innovus, VHDL Programming, Verilog-A Programming, C (Programming Language), Very-Large-Scale Integration (VLSI), Field-Programmable Gate Arrays (FPGA)