Mayank Baunthiyal

Next generation GPU architecture - Hardware and Software Co-Design.

Performance Architecture Lead for next generation Cache Coherent Interconnect. Focussed on delivering !/$ for AI/ML workloads. Architecture Lead/Manager for Cache Coherent Interconnect for Vera SOC. Architecture Lead for Last Level Cache and Coherency Protocol for Thor SOC. RTL Design and Coherency Architecture for Grace SOC.

- One of the technical lead on Fetch and Decode for bleeding edge Nvidia CPUs. - Led design for Micro-op cache. - Contributed to architecture and microarchitecture decisions across entire CPU frontend.

- Technical leads on level-2 cache. - Led design and architecture decisions. - Owned coherency logic RTL.

- RTL design-owned coherency pipeline for the level-2 cache. - Contributed towards architecture/design and led many functional feature development. - Pre-silicon performance debug and correlation with RTL. - ECO implementation and timing fixes. - Formal verification of coherency protocol.

Perf/Watt architecture for Nvidia CPUs

Marketing Research.

Worked at Defense Electronics and Application Laboratory as Intern. Worked on establishing FPGA communication with host PC over USB channel. Implemented a DSP design on FPGA and controlled it using a custom developed host PC application.

Developed a embedded system based frequency generation circuit using AT8951 microcontroller.

Worked at the Geodata Processing and Interpretation Center. The task was to identify newer and more reliable storage technologies to ensure efficient and effective storage of data. The project also looked in to benefits of Storage Area Network for the above requirement.

1) Project on 'Simulated Annealing'​ based partitioning of a chip in C++. 2) Developed a 16 bit Kogge-Stone adder in 45nm technology(Cadence, Hspice, Cosmoscope and Calbre). 3) Developed a 2Kbit SRAM in 45nm technology(Cadence, Hspice, Cosmoscope and Calbre). 4) Designed a adaptive FIR filter in Verilog and perform verification, testing and optimization. 5) Project on proposing hardware requirements to support 'Dynamic parallelization of single thread on Multicore processors.'​ Based on a paper by Intel. 6) Developed a peer-to-peer file transfer system as part of socket programming project. 7) Lab work at Nano Fabrication Center at UMN. Fabricated transistors, resistors and ring oscillators on a wafer. 8) Presented a paper titled "Fabricating Three Dimensional Integrated Circuits and Solving Cooling Issues." 9) GPGPU to expedite IP address lookup for the software routers.

1) Seminar on Aviation Technology. 2) Seminar on Missile Guidance. 3) Major project on speech recognition Robot(MATLAB and AT8951). 4) Minor project on database management(C++). 5) Microcontroller 8051 interfacing and programming. 6) Microprocessor 8085/8086 interfacing and programming.