Max Mah B.

- Led Complex NPI & HVM Manufacturing Programs Across Board, Tester Products - Led & Integrated Cross-Functional NPI Integration program into High Volume Manufacturing (HVM) - Chaired Cross-Org Manufacturing Teams meeting to drive DFX, Testability & Readiness - Defined and Executed Multi-Phase Program Strategies (New Product Introduction - NPI, First of Kind - FOK, Material End Of Life - EOL) - Developed & Maintained NPI Roadmaps Aligned to Business and Factory Strategy - Built Systems, Structures & Governance for Program Execution - Collaborated with R&D, TD, ATM VF, Ops, and Supply Chain Partners - Managed Program Financials, Risk, and Change Control - Executed Technical Leadership in Product Development & Transfer - Ensured Manufacturing Documentation, System Readiness & Compliance

- Started as senior system integration | mfg technologist that managed and sustained mechanical assembly integration documentation, bill of materials (BOM) for new product and repurposing - Key interface with R&D stakeholders, assembly & test manufacturing (ATM) partners and leadership internally to ensures the overall program performance against schedule, monitors progress and takes remedial action as appropriate - SPOC on FOK program, involvement in pathfinding and development stages - Exercises judgment and discretion to ratify the developed solutions from team/cross functional areas, remove obstacles and redefine approaches where deemed required throughout the product life cycle (PLC) - Chaired to mfg change control board. Disposed engineering changes & avoid any disruption - Managed a high performing and diversified system integration engineering team that focused on development of manufacturing capability, scalability, new product introduction, engineering changes, quality and continuous improvement of class, burn-in & system validation boards and testers assemblies - Championed design-for-assembly & manufacturing (DFA & DFM) on new product transfer. Managed jig and fixture development, and process definition for board and assembly integration—driving yield improvement towards high-volume readiness - Led NPI builds and transitions across multiple products (instruments & testers), manufacturing assembly lines, aligning resources, schedules, and cross-functional deliverables to ensure seamless ramp to high volume manufacturing - Introduced Lean practices (5S, Kaizen, Standardized work, KPIs, PDCA & Root cause analysis with structured problem solving) across engineering workflows to enhanced productivity, reduced waste and quality issues - Developed forecasts & resource plans for product ramp & new product transfer - Mentored & developed engineering teams in matrixed environments. Fostered a culture of continuous improvement, ownership, and technical excellence

- Evaluation, debug and file design bugs to get design fixes of new test program released - Wrote and verified test content to improve test coverage for integrated circuit - Reiterate emulation for cluster test and verified root cause from test environment or test content - Improve ported test passing rate until all features and structure is fully completed - Led CPU tile team to prioritize and deliver test porting passing rate goal - Report weekly progressive status to product owner through SCRUM processes

- Involvement in validation of the initial design coding (RTL - in system Verilog format) and drafted a design plan which includes identification of the design complication and risk area. Consulted and worked with RTL coder/design architect consistently in design plan perfection - Utilized random logic synthesis (RLS) design tool to construct very large integrated circuits. Involved intensive in RLS tool debug/fine tune/scripting throughout design construction process to maximize the quality of the output. This will ensure minimum manual works post RLS flow - Worked on post RLS flow include electrical rule check (ERC) correction, reduce power leakage, improve signal slope, Cmax violation and max/min violation - Utilize Unix, Perl, formal equivalent verification (FEV), flow manager (FM), synopsis IC compiler and Snakes schematic editor to converge timing, noise and power before the design of new chip can be taped in - Worked CPU interconnect (IC) to improve functional unit block and intersections wire connectivity quality. This task involves intense collaborative among other sections design for trade off requirement to achieve section IC quality. Section IC quality is a must requirement to full chip tape in - Fub-functional unit block is a smaller design area that partitioned by sections in a full chip for design efficient purposes

- Specialized in Die Prep, Wafer saw & Tape and Reel Die Sorter (TRDS) process. Group leader that chair cross functions between R&D and HVM team - Utilized input/output analysis in process specifications for process modelling to predict potential failures and acquired Six sigma Failure Mode Effect & Analysis (FMEA) in process development to simplification and reduced overall development time to HVM - Contributed to substantial technical papers submission and awarded 1 US Patent on thin wafer process. Reference number: 8124471 - Managed and forecasted the budget to use on new capital/non-capital and materials needed for future machine - Utilized JMP statistical method tool and design huge number of designs of experiments (DOE) throughout development cycle to identify process windows, statistical control/spec limit - Utilized Process Control System (PCS) methodology through Statistical Process Control (SPC) to analyze and control key machine parameters and improve process margin - Responsible in machine’s time study to provide accurate runtime, MTBA & MTBF to have precise number of machines in HVM - Experienced in leading root causes in quality events (Die chip/crack/damage losses). Utilized mechanical, electrical and statistical analysis to proof the concept which eventually resolved the high yield loss occurrence