Marri Akhil

Actively involved in performing Block-level Synthesis using Genus-Cadence synthesis tool for various GPU designs including Logic and Power optimizations.

Worked as a Graduate Services Assistant under Prof. Andrea Richa for CSE 551 - Foundation of Algorithms

Project 1: {Updates Required} Working under Prof. Umit Ogras Title: Domain-specific System on Chip Implementation, This Project is funded by the U.S. Department of Defense’s - (DARPA) Defense Advanced Research Projects Agency under the Electronics Resurgence Initiative. Project Objectives: 1. Designing a Domain Specific System on Chip (DSSoC) that will create a development ecosystem that takes advantage of the specialized hardware with no added burden to the programmer. 2. Design an intelligent scheduler for efficient data movement between DSSoC processor elements. 3. Build a DSSoC of advanced, heterogeneous processors and accelerators for software radio. Responsibilities: (Current) 1. Developed a set of accelerators such as Scrambler, Convolution Encoder, Viterbi Decoder and Schedulers which helped in improving the power by 25% if the accelerators were implemented on the ARM cores standalone. 2. Designed an effective Scrambler accelerator that helps to improve the overall execution time (including communication time) from 43.37us to 2.29us to transmit 120 bits of data. 3. Created multiple applications that would parallelize multiple tasks and improve the performance of the overall project by 14%. 4. Sniffing the AXI Communication protocol interface that helps the ARM cores to communicate between the cores and helps ARM cores to communicate with the designed accelerators.

Worked as a grader for CSE434 - Computer Networks under Prof. Duo Lu

Project 2: (Final Stage) Title: Per-Core Power Modelling for Huawei Nexus 6P Smartphone. Tools Used in this Project: 1. Huawei Nexus 6P Phone 2. NI PXIe-1071 Data Acquisition System Key Responsibilities: 1. Analyzed the Power consumption on a Huawei product - Google Nexus 6P using National Instruments Data Acquisition System (NI-DAQ). 2. Developed per-core power models for each major component in Snapdragon 810 Soc heterogenous System-on-Chip. Research outcome: This Research project deals with the per-core power modeling methodology and its application to Huawei Nexus 6P smartphone. We present power consumption models for the (1) display, (2) big core cluster, (3) little core cluster, (4) GPU, (5) CPU memory controller, and (6) GPU memory controller. The power models are developed by performing power consumption measurements and performance data collection while running representative benchmarks at varying temperature and operating frequencies. The proposed models predict the total power consumption with only 8% error on average. Future Research Directions: We plan to implement these power models in power management drivers. This will enable us to predict the impact of power management decisions, such as increasing the frequency of a given PE, at runtime. Then, we will use these predictions to manage the power states of all PEs using in a coordinated fashion using reinforcement learning, in contrast to current practice that employs independent power management drivers.

Associated with Reliance jio for Incident Fault Management (IFM) in Network Service operations (NSO) at Network Operation Centre (NOC), NHQ Mumbai. Key responsibilities are: 1. DWDM & OTN Transmission (10G and 100G Network). 2. Network Alarm Monitoring and its Restoration. 3. Network Channel & Hardware Monitoring. 4. Coordinate and support the field engineers for clearing alarms and hardware faults on equipment’s, Alcatel Lucent (ALU PSS-32 & ALU PSS-4) and Ciena (Shelf6500 & DXC5430), 5. Assuring proper transmission at NMS and EMS by giving Operation and Management (O&M) Support at Network Operation Center (NOC). 6. Configuring services for Tejas POI in SDH media and managing the performance of hardware equipment’s, ALU PSS-32 and Ciena DXC5430 by Fault Tracing (FT).

1. Assisted students in performing their IC Design engineering laboratory work with software module such as CADENCE (Virtuoso design products), Multisim ver. 10, Altera Quartus II (for RTL Synthesis)etc. 2. Helped professor in carrying out various administrative process such as preparing resources for teaching, evaluating assignments, assigning grades and helped the professor in assigning various project topics to students.

Implemented a solution for tracking a signal under high dynamic scenario, High Dynamic Carrier Tracking loop by understanding the concepts of COASTAS Loop and Doppler Effect.

CORE Subjects: 1. VLSI Design 2. Computer Architecture 3. Constructionist Approach to Microprocessor Design 4. System-Level Design for Multicore Architectures 5. Digital Circuits and Systems 6. Foundation of Algorithms 7. Random Signal Theory 8. Computer Network Security 9. Artificial Neural Computation

Key Courses: Computer Architecture, VLSI System Design, Digital System Design Digital Signal Processing, Digital logic Design, Digital Communication, Introduction to Nano Science and Nano Technology