Manju Arora

Sr. Engineering Manager @ Intel Corporation

About

Experienced Engineering leader with expertise in pre-silicon design/verification, emulation and post-silicon debug for complex high-performance server products. Built and ramped high performing teams to deliver on complex roadmaps. Passionate about growing and developing talent through training/mentoring programs. Led cross-site teams responsible for validation of complex DFT within server microprocessor design. Responsible for technical direction setting, planning and execution of DFT design and validation activities as well as ATPG/Functional/Array content delivery on multiple Xeon products. Proven ability to build and equip high performance teams. Excel at building and maintaining partner/customer relations. Skills/Highlights • Strong technical skills balanced with managerial. • Experience managing multi-site and matrixed teams. • Excellent communication and influencing skills • Experience in managing risk and prioritizing task and resources. • Strong experience both as a people and project/program manager • Strong experience in DFT, post-si and HVM • Experience managing multiple functions and multiple products in parallel. • Managed teams of 15-18 engineers with varied levels of experience. • Passionate about enhancing efficiency through automation. • Adept at fostering and sustaining business relationships.

Country

United States

City

Santa Clara

Industry

Semiconductors

Skill

DFT, Debugging, ATPG, Testing, Microarchitecture, SoC, VLSI, Verilog, RTL design, Static Timing Analysis, IC, Semiconductors, EDA, ASIC, Functional Verification, Specman, Processors, Logic Design, Silicon, SystemVerilog

Experience

Sr. Engineering Manager

Intel Corporation

2019-12 - Present · 6 yrs 10 mos

Santa Clara County, California, United States

Managing multi-function teams in the areas of DFT, Reset, Fuse and Pattern translation functions for HVM (High Volume Manufacturing) with teams based across multi-geographies. These functions are the first in line (enablers) for all HVM content teams. Driving multiple products in parallel on Intel’s Xeon roadmap all at different phases ranging from early design to post-silicon all with a lean team.

SOC Engineering Manager

Intel Corporation

2016-6 - 2019-12 · 3 yrs 7 mos

San Francisco Bay Area

Led cross-site teams in the areas of high-performance server processor DFT Design, Validation and ATPG. Responsible for technical direction setting, planning and execution of all DFT pre-silicon design and validation activities on multiple IP’s for the Xeon processors. Proactively evaluated scope, assessed progress, adjusted assignments, closed on dependencies and managed risks resulting in delivering high quality and a stellar-on-time record. Drove DPM improvement initiatives to improve product quality.

Senior DFT Engineer

Intel Corporation

2009-7 - 2016-6 · 7 yrs

Senior DFT Engineer with in-depth knowledge and hands-on experience on the complete DFT cycle. - Lead verification of multiple DFT features. Strong understanding of standards like IEEE1500, IEEE1149.1 and BIST. Hands-on experience in Functional Verification, ATPG, pattern generation, fault grading and post-Si debug. - Experience with silicon bring-up and post-silicon support/debug activities on ATE. - Experience in creating feature specific test plan for high functional coverage of multiple features on multiple projects. - Built models and generated collaterals for ATPG pattern generation. - Collaborated with test and product engineers to ensure product is testable and has high level of coverage during production test and can be pushed to production release.-