Mahdi Changani

- Designed and implemented FPGA firmware for video interface conversion (SDI, CSI, HDMI RX/TX). - Developing 4K 60Hz ISP and video pipeline on Zynq Ultrascle Kria board. - Developed a custom AXI-based video mixer IP handling 4x simultaneous inputs/outputs. - Integrated MicroBlaze soft processor to manage FPGA video flow, achieving 99.99% uptime. - Created custom VHDL IP cores for converting non-standard video streams to AXI format. - Optimized resource utilization, reducing FPGA logic usage, power, and BOM cost. Key Relevance: - Clock and reset strategy design for video pipelines. - AXI4 interface integration. - Timing closure and SDC constraint optimization. - Use of Vivado Integrated Logic Analyzer (ILA) for debugging. - RTL design in VHDL/Verilog. - TCL automation for builds. - Bash scripting for build and verification. - Hands-on FPGA lab debugging (oscilloscope, logic analyzer).

- Designed FxBlox SBC hardware based on Rockchip RK3588 SoC with below features: - 8GB or 32GB LPDDR4/4X, 16GB eMMC and 16MB SPI Flash. - B and M Key M.2, and it supports Both SATA and 4x lane PCIe. E Key M.2 for Wi-Fi. - 3x USB3 Type-C with DP alt-mode and 1x USB2 Type-C. - Ported and Customized Armbian OS for RK3588. - Developed and maintained Bootloader (U-Boot), Linux kernel , and Device Tree. - Implemented USB-based firmware update flow in U-Boot for field upgrades. Key Relevance: - SoC integration experience. - Top-level system design and validation. - Firmware and hardware co-design on SoC platforms. - Deep knowledge of SoC boot flow, reset domains, and timing. - Proficiency in Linux-based workflows and Git version control.

- Ported multiple Ethernet phy drivers for custom ZYNQ and ZYNQ MPSoC using PetaLinux tools. - Developed AFDX-compliant Ethernet MAC IP in VHDL for deterministic communication. - Designed FPGA Ethernet interfaces with RGMII, SGMII, SFP, SFP, 10G Interfaces. - Designed an FPGA Ethernet switch soft IP core using VHDL and HLS. Key Relevance: - Strong experience in FPGA-based networking IPs (Ethernet, AFDX, SGMII). - Verification using Vivado Simulator. - Timing and clock-domain crossing (CDC) design. - RTL testbench development. - Top-level FPGA integration and block design in Vivado.

- Led a multidisciplinary team of hardware and firmware engineers. - Developed Linux Kernel, U-Boot and Rootfs using Yocto for Custom NXP iMX6 SoC. - Firmware developed for Microblaze, STM32 and ZYNQ Processors. - Firmware programming for various interfacing such as RS232, RS422, RS485, CAN, Ethernet. - Designed a multi-channel PIC MCU mass programmer with Xilinx Spartan6, reducing production time 100×. Key Relevance: - SoC-level experience (Zynq, i.MX6). - Firmware–FPGA integration. - Team leadership and verification strategy definition. Hardware validation using lab instruments (oscilloscope, logic analyzer).

Firmware design for the electric door with STM32F105 MCU Control DC motor speed with PWM and PID controller. graphical LCD for setting the menu with custom Persian font due to low chip. memory and USB Flash bootloader along with the encrypted update. Intelligent obstacle detection and Implementation of automatic door and course type identification algorithm and adjustment of opening and closing differences https://extra-se.com/wp-content/uploads/2022/01/EX2020.pdf

Develop FPGA Evaluation hardware and IO carrier card for interfacing digital and analog interfaces. Instructor of Embedded System training course with ZYNQ Instructor of Microblaze processor with Spartan6 FPGA

Development of Linux operating system. Implement and customize the Linux operating system for Allwinner SoCs. Instructor of Linux training course using Cubie board. Designing Cubik, Custom Debian Distro, for Allwinner boards with auto-configure (shell script) with support for all types of LCDs and touch screens.