LuYung L.

TF TD department @ 芯恩（青岛）集成电路有限公司

About

● 9年薄膜工艺开发经验(力积电/晶合/晋华/芯恩) ✓ 熟悉PVD Cu barrier/Al sputter/NiSi/CoSi/TTN 相关/ECP Cu plating/W相关. ✓ 熟悉CVD BD low K/HARP/CESL/TEOS/APF/NDC/SiH4 base dielectric. ✓ 开发国产机台Naura HP annealing system/HM_TiN/ALD TiN/ALDHK. ✓ 开发国产机台拓荆300T PCS, EX系列及XKL PECVD TEOS/USG/SiN. ✓ 熟悉后段铜制程填洞改善, 电性优化及可靠性改善. ✓ 评估新制程,新机台及原物料评估能力. ✓ 现况解析及解决制程问题能力. ✓ TEM, SEM, EDS, XRD 分析. ✓ 具有良好协调沟通能力,具有极佳团队合作能力,懂得利用个人能力发挥团队力量. ✓ 具有全盘视野解读及解决薄膜工艺所有问题. ● 6年CMP 工艺量产经验 (联电) ✓ 熟悉150nm~90nm STICMP/OXCMP/CUCMP 工艺. ✓ Release 130nm Cu RFMD SOI STICMP制程.

Country

City

China

Industry

Semiconductors

Skill

工程, 製程

Experience

TF TD department

芯恩（青岛）集成电路有限公司

2022-10 - 2025-7 · 2 yrs 10 mos

✓ 40HV薄膜开发: ->HARP 相关case改善, STI/ILD void study 及defect 改善. ->Contact TTN bevel peeling taskforce owner,藉由charging model/bevel oxide remain step by step check 找出关键改善工艺. ->Passivation TEOS PMOS PID fail, 藉由TEOS 及USG tuning 找出改善方式 ->各项defect CIP 上线,包含go clean/x clean帮助后期良率提升. ->BEoL warpage藉由USG/SiN stress tuning确保litho GLC pass. ->国产机台评估包含拓荆PCS/300T EX, XKL TEOS/USG/SiN. ->LCOS特殊工艺后段HDP填充工艺改善. ->研发项转移量产护航. ✓ 28+ 工艺开发: ->FCCSP ELK crack后段low K/NDC相关工艺recipe CIP 及adhesion/bump pull test. ->CESL SiN小管路NH3 改造for Rs decay issue. ->NBTI ALDOX study for 28+平台特殊工艺 ->MIM 漏电改善藉由氮化钛roughness改善. ->XKL/拓荆 TEOS/USG/SiN国产机台评估. ->华创TiAL/拓荆FCVD评估后期追踪. ->研发项转移量产护航.

Project team section manager

Jhicc

2021-7 - 2022-9 · 1 yr 3 mos

1.特殊型鐵電記憶體開發 2.國產機台評估 3.各項開發KPI達成

Section Manager

Jhicc

2020-4 - 2021-7 · 1 yr 4 mos

中國福建泉州

1.N1X generation TF PVD 1st BKM develope 2.国产机台评估及去美化评估

副理

Nexchip

2018-7 - 2020-4 · 1 yr 10 mos

中國安徽合肥

1.Set-up 1st Cu-line of Nexchip for 80nm/55nm. 2.Through depart manager (Bucky chen) lead to set-up 80nm BEoL flow and installation new tool for 55nm process. ->Deliver 1st BKM of HARP / CESL SiN / Ni-Pt / BD1 / NDC / CuSPUT and ECP. 3.MIC tool investigation for 80nm/55nm/110nm. ->Naura HP annealing system/HM_TiN/TiN/Al/barrier seed. ->Piotech dielectric oxide film/SiN ESL/DARC. 4.80 HV/55nm raw material evaluation. 5.80 HV/55nm all tool NPW rule set up.

Senior Engineer

United Microelectronics Corporation (UMC)

2012-9 - 2018-6 · 5 yrs 10 mos

Hsinchu City, Taiwan, Taiwan

1.High step-height loading for OXCMP less deposition/less polish to improve U% and WPH~30%. 2.RFMD SOI process APC model set up to prevent over polish. 3.IVT PAD evaluation for cost down and edge Cp improve. 4.SPC coordinator to handle TF all inline/ED alarm case and issue improve. 5.2 poly prod. defect/CP improve (dense area SiN residue) use high down force RCP. 6.Nano measure tool special film stacking set up no need vender support. 7.CMP close loop control for WTW Cpk improve<1.67. 8.Flatness model set up for 1.5 times step height OX removement.

Staff Engineer

力晶科技股份有限公司

2010-8 - 2012-8 · 2 yrs 1 mo

台灣新竹市

1.Cobalt process tool transformation from DRAM to foundary BSL. 2.Logic product necessary for Cu process do MOCVD chamber verify. 3.SIP gap fill process arcing issue need to be scraped, adjust DC power arcing trip limit can improve this case~75% 4.SIP target 2nd source evaluation to modify target shape and extend target life~1000kw/hr.