Liang Xue
System Level Testing Engineering Manager @ NVIDIA
About
Silicon Product Engineering professional with comprehensive pre/post-Si expertise including power/performance/thermal, binning, yield, characterization, NPI, and high-volume production. Passionate in driving methodology transformation through a first-principles approach to the operation.
United States
Cupertino
Semiconductors
Engineering Management, Engineering Leadership, System Level Test, Product Engineering, Power Performance Binning, High Volume Manufacturing, NPI, Agile Methodologies, Data Analysis, Semiconductors, DOE, SPC, Process Engineering, SQL, Labview, JMP, SoC Power Model, SoC Thermal Model, Lithography, PECVD
Experience
System Level Testing Engineering Manager
NVIDIA
Santa Clara, California, United States
- SLT Test Methodology - SLT Characterization
System Level Testing Product Engineer
NVIDIA
Santa Clara, California, United States
- SLT product lead for GPU products. - Lead NPI, yield, characterization, and production ramp activities.
Pre-Silicon Binsplit Engineer
Intel
Portland, Oregon, United States
- Pre-Si binsplit model. - Product definition. - Power Performance Thermal analysis.
ATE Final Test Product Development Engineer
Intel
Portland, Oregon, United States
- ATE power speed binning flow. - Yield enhancement.
ATE Wafer Sort Product Development Engineer
Intel
Portland, Oregon, United States
- Wafer sort NPI, yield, and production ramp.
Fab Process Engineer
Intel
Portland, Oregon, United States
- CVD process development, yield, and production ramp.
Education
The University of New Mexico
Optical Science and Engineering
Zhejiang University
Optical Engineering
Liang Xue's Contact Information
Phone
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