LEE ZHAO TIAN
Design Verification Engineer @ Intel
Malaysia
Johore
Information Technology & Services
Printed Circuit Board (PCB) Design, EasyEDA, High-Speed Signal Design, Component Placement Optimization, Design for Manufacturability (DFM), Power and Signal Integrity Management, Thermal Management, Electromagnetic Compatibility (EMC) Design, Advance Low Power Design, Unified Power Format (UPF), Creative Problem Solving, Team Leadership, Teamwork, Red Hat Linux, Vi editor, Verilog HDL, SystemVerilog, Synopsys IC Compiler, Synopsys Design Compiler, Synopsys Primetime
Experience

SOC Analyst
Shah Alam, Selangor, Malaysia
Cybersecurity Tools and Technologies: Proficient in using SIEM (Swimlane, USM AlienVault), EDR (SentinelOne), SOAR, vulnerability management tools (VScan), and antivirus software (Trend Micro). Security Concepts: Deep understanding of cybersecurity principles, including threat detection, incident response, malware analysis, data breaches, DNS security, and cloud security. Incident Management: Skilled in handling and responding to various security incidents, including ransomware, phishing, and data leaks. Alert Management: Fine-tuning alert systems, reducing false positives, and prioritizing high-severity incidents. Automation: Proficient in automating tasks using tools like Microsoft Outlook and scripting languages to improve efficiency and reduce manual workload. Reporting: Ability to generate clear and concise reports for clients, summarizing findings and recommendations. Continuous Monitoring: Experience in using tools like Cyber Threat Map and Site24x7 to monitor for threats and ensure system availability. Collaboration: Strong teamwork skills, working effectively with colleagues in a collaborative SOC environment. Problem-Solving: Ability to analyze complex security issues, identify root causes, and implement effective solutions. Adaptability: Quick learner and adaptable to new technologies and tools.
Education

National Semiconduxtor Excellent Program (NSEP)
Enhanced my digital design and verification expertise through the National Semiconductor Excellence Program (NSEP). Proficient in: Verilog HDL design and implementation SystemVerilog verification environment development Simulation and debugging using Synopsys VCS Synthesis and optimization with Design Compiler (timing, area, power) Design for Test (DFT) insertion and DRC fixing Low-power design techniques (multi-threshold, multi-voltage, power-gating) using UPF Static Timing Analysis (STA) with PrimeTime Place and Route using IC Compiler II
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