Lee-eun Yu
Staff Design Engineer @ Micron Technology
About
- 3D NAND Flash Circuit Design Engineer - Performance improvement for 2D and 3D NAND Flash devices - Page buffer and row decoder design for 3D NAND Flash - Abundant hands-on experience with NAND Flash testing, C/C++ and script language programming
United States
San Jose
Semiconductors
C/C++ Programming, HSPICE, Script Language (TCL), NCSIM, Chip Testing using P300 (FPGA-based NAND test solution), Magnum Programming, Mass Data Management Tool (Spotfire)
Experience
Staff Design Engineer
Micron Technology
San Jose, California, United States
- NAND core design engineer - Page buffer and row decoder design and verification - Performance optimization via silicon measurement - Performance estimation using calculator
Senior Design Engineer
SK hynix
South Korea
- NAND core design engineer - Page buffer and core algorithm design for 128-Layer 1Tb TLC 3D NAND Flash - Silicon level design verification - Performance optimization from Silicon measurement
Junior Design Engineer
SK hynix
South Korea
- NAND core design engineer - 72-, 48-, 36-Layer TLC 3D NAND Flash performance improvement - Set up P300 based chip-level testing environments using C/C++ programming - Executed extensive chip-level testing focused on performance optimization - Fundamental technology development for NAND Flash performance enhancement including bit line’s current consumption estimation method, programmed Vth distribution estimation tool, innovative program pulse shape for improved performance
Research Assistant
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
Education
Korea Advanced Institute of Science and Technology
Electrical and Electronics Engineering
Korea Advanced Institute of Science and Technology
Electrical and Electronics Engineering
Thesis: A Study on Two-dimensional Next-generation Non-volatile Memories
Korea Advanced Institute of Science and Technology
Electrical and Electronics Engineering
Lee-eun Yu's Contact Information
Phone
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