Lawson Z

Responsible for the RTL design and micro-architecture implementation of specific sub-modules within the AI accelerator (NPU). Handled daily tasks including RTL coding, Lint/CDC checks, and fixing logic bugs reported by the verification team. Collaborated with the architecture team to implement hardware features based on defined specs. Participated in the synthesis and timing closure process for the assigned blocks to ensure they met the project's physical constraints and power targets.

Focused on the digital logic design and integration of standard IP cores (such as GPIO, I2C, or UART) and Bus interfaces within the SoC. Worked on basic power domain partitioning and implemented clock-gating logic to manage power consumption. Provided technical support for the verification and physical design teams during the chip development cycle. Maintained design documentation and assisted in debugging FPGA prototypes and post-silicon issues.