Lahari Puralachetty

Staff Engineer @ Qualcomm

About

-Experienced block-level GPU Design verification engineer -Developed reusable Verification Environments(UVM). -Code and Functional Coverage closure -Worked on Mixed Signal IPs like USB3.0 PHY ,PCIe PHY ,SATA PHY ,DP and SGMII. -Good knowledge on PHY Protocols : USB , PCIe and SATA. -Working knowledge of AMBA protocols(AXI,APB and AHB). -Working knowledge of Python Tools familiar with: -Specman,NCSIM,IMC,Incisive Formal Verifier,Vmanager,VCS,Verdi,Xilinx ISE ModelSim,Vplanner Languages known: -Specman-e,System Verilog,UVM -SV,C,C++,Verilog,VHDL,Working knowledge of PERL ,Python and SHELL Scripting(Capable of working on Unix OS).

Country

City

United States

Industry

Semiconductors

Skill

Specman e, UVM e, Verilog, VHDL, Testing, Perl, C++, Data Structures, C, Unix, Integrated Circuit Design, VLSI, ModelSim, Silicon, Structural Testing, Structural Testers, Python, System Verilog, Universal Verification Methodology (UVM)

Experience

Staff Engineer

Qualcomm

2018-1 - Present · 8 yrs 9 mos

Santa Clara, California, United States

-Verification of High-Level Sequencer for Shader processor Develop UVM testbench Code/Functional coverage closure C++ based checker developement -DV lead for Low-Resolution Z filtering block (2018 - 2020)

Senior Design Engineer

Cadence

2014-6 - 2017-2 · 2 yrs 9 mos

Bengaluru Area, India

1. Functional verification of PHY (USB 3.0/3.1,PCIe,SATA,DP,SGMII) both RTL and GLS.Capable of doing both RTL and GLS debugs.Worked on both IP verification and testchip verification. 2.Developing reusable multi-link/multi-lane verification environments in UVM-e. 3.Responsible for Code and functional coverage closure. 4.Creating Vplans. 5.Connectivity Verification using IFV 6.Scripting in PERL for automation to reduce manual effort 7.Code and functional coverage closure,Coding assertions in Specman-e.

Graduate Technical Intern

Intel

2013-5 - 2014-6 · 1 yr 2 mos

Bengaluru Area, India

Developed test content to meet the fault coverage of Intels Advanced Graphics Processor. Fault grading of the developed tests. These tests facilitate Post Silicon Validation Process to test for manufacturing defects on the silicon. Scripting in PERL.