L Karthik

Project - Taura Description: Flip Flop count : 1000 k Duration : Aug 2025 - Present Technology : 6 nm Tools Used : Genus, Design Compiler, Tessent Scan, Primetime, Conformal LEC, Conformal CLP, Tessent Shell, Time Vision Team : DFT Insertion, Synthesis, DFT/Functional Validation and Prelayout STA Roles and responsibility: 1) Single Corner and MMMC Early Physical Synthesis (EPS) using Genus. 2) Single Corner and MMMC Physical Aware Synthesis on PD Floorplan using Genus. 3) Scan, EDT, and OCC Insertion using DC. IJTAG and SSN Insertion using Tessent Scan. 4) RTL to Netlist and Netlist to Netlist FV using Conformal LEC. 5) ATPG chain trace, DRC clean up and coverage analysis for SA, TDF using Tessent Shell. 6) Netlist low power checks using Conformal CLP. 7) SDC quality check for functional and DFT modes using Time Vision. 8) CTS Sanity Check for functional and DFT modes using Primetime. 9) Prelayout STA to check no clocks, unconstrained end points, RC annotation, signal integrity, slack and latency with help from STA team. 10) Fixing setup, hold, trans, and cap violations using tweaker with help from PNR team. Project - PNC Description: Flip Flop count : 2000k Duration : Oct 2024 - July 2025 Technology : 10nm Tools Used : Tessent Shell and Verdi. Roles and responsibility: 1) ATPG for TDF, cell aware and dport. 2) Coverage improvements for stuck-at and at-speed. 3) Implemented DFT ECO’s. 4) Automated manual tasks using bash shell scripting. 5) Tweaks in ICL/PDL for ATPG (wrapper chain disable, PLL chain disable, bypass).

Deputed to Excelmax Technologies by parent company Ziotron Consulting. Project Name - Nords AU: Client: Qualcomm (Through Excelmax Technologies) Description: Flip Flop count : 1500k Duration : Apr 2023 - Till date Technology : 10nm Tools Used : Fast Scan, Verdi, Conformal LEC, Tetramax, Genus, Innovus Roles and responsibility: 1) Scan insertion and DRC clean up using Tessent SSN. 2) DFT Stitch and DRC clean up using Genus. 3) Formal Verification between scan insertion and synthesis. 4) XLBIST ATPG Trace and X2 DRC clean up using Tetramax. 5) XLBIST Pattern generation and coverage improvement for stuck at. 6) Got targeted coverage of 85% for XLBIST stuck at ATPG. 7) XLBIST Zero delay simulation using Verdi. 8) Implemented ECO’s in Genus and Innovus.

Description: Flip Flop count : 1200k Duration : Sep 2022 - March 2023 Technology : 10nm Tools Used : Fast Scan, Verdi, Conformal LEC, Spyglass, Tetramax, FC Roles and responsibility: 1) Scan insertion and DRC clean up using Tessent SSN. 2) DFT Stitch and DRC Clean up using FC. 3) Spyglass based DRC check and clean up on stitched netlist. 4) ATPG Trace and DRC Clean up using Tessent Shell. 5) Coverage improvements for stuck-at. 6) Got targeted coverage of 99.2% for stuck-at. 7) Zero delay and timing simulation using Verdi. 8) Implemented ECO’s in DC and FC.

Project - GUNDERSON ROCK ARCHITECTURE Deputed to Cerium Systems by parent company Ziotron Consulting. Client: Intel Description: Flip Flop count : 1750k Duration : Oct 2021 - Aug 2022 Technology : 16nm Tools Used : Tessent Shell and Verdi. Roles and responsibility: 1) ATPG for Stuck at, TDF and bypass (stuck at). 2) Coverage improvements for Stuck-at & at-speed. 3) Got targeted coverage as 98.8% for stuck-at and 90% for At-speed. 4) Performed zero delay and timing simulations. 5) Simulation debug for parallel and serial patterns.

1) Content creation, review and correction of lecture notes for Electrical Engineering subjects such as Principles of Electric Circuits and Understanding the National Electrical Code.

1) Creation of lecture notes and PPT’s for Signals & Systems, Digital Signal Processing, Analog Electronics, Digital Electronics, Basic Electronics, and Basic Electrical. 2) Creation of step by step solutions for the exercise problems of the subjects mentioned in 1).