koti reddy

physical design and verification engineer

About

An enthusiastic and self-motivated experienced Physical design engineer looking for a challenging and responsible position as Physical design engineer to apply my knowledge and skill with my hard work and patience,and be world class in ASIC design.

Country

india

City

bengaluru

Industry

semiconductors

Skill

digital electronics, analog circuit design, c, debugging, pcb desigining, sales, pcb design, analog, electronics, asic, vlsi, verilog, microcontrollers, integrated circuit design, usb, designing the electronics ckts, cadence, cmos, testing, fpga, servicing, vhdl, modelsim, c++, testing electronics circuit, semiconductors, simulations, pspice

Experience

physical design trainee

rv-vlsi design center

2017-3 - 2017-9 · 7 mos

Block Level Implementation Of Lakshya Sub System Description : Block level implementation of lakshya sub system.Scaling technology : 40nm, Macro count - 34, Standard cell count-38887,Area - 4.2 mm2,Supply Voltage : 1.1,power budget : 600mW ,IR drop < 55mV, Metal Layers : 7. Tools : IC Complier from synopsys Challenges : Floorplanning - The main challenge of this project was to design floorplan. The floorplan should be such that it doesn't violates the IR drop requirement. Power Planning- During the power planning the main challenge was to get the tracks placed properly without any overlaps, missing tracks. The pitch and step must be well maintained. Routing Congestion - The routing congestion removal is done by analyzing the routing congestion and need to increase macro spacing accordingly to get the congestion to lowest value

cse

jet inks

2014-7 - 2017-1 · 2 yrs 7 mos

* Performing installation, Testing & Troubleshooting the industrial inkjet printers. (Like Domino,Markem Imaje,Videojet,T&B). * Improving machine uptime by developing statistical studies & maintenance action plans. * Wide experience as instructor and technical advisor of formal training to engineers. * Organized monthly client meetings in order to report performance status. * Allocating work to engineers. * Daily Engineers work status Updating to management . * Expertise in cost and engineering responsibilities. * Expertise in following safety guidelines and procedures.

physical design and verification engineer

intel corporation

2017-10 - Present · 9 yrs

diploma trainee engineer

nokia

2011-8 - 2012-9 · 1 yr 2 mos

* Hardware testing in mobiles (BUI-Basic User Interface testing) like: Audio,RF testing,Camera,Display,keyboard GSM&NSM, Bluetooth etc. * Preventive Maintaining(PM) the test setup using CLRI method. * Troubleshooting of Industrial PC & Desktop PC. * Reducing MFR (Manufacture failure rate) & Downtime. * Trouble shooting in Barcode printers & Scanners. * Trouble shooting in Hardware & Networking.