Koteswara Sai Krishna Ogiboyina

• Led the physical implementation of multiple IPs from Netlist to GDS, optimizing floor planning, placement, CTS, routing, RC extraction, timing closure, and low-power solutions for successful tape-out. • Implemented hierarchical design planning and partitioning with a bottom-up approach, enhancing efficiency for complex systems. • Achieved 15% PPA (Performance, Power, Area) improvement on multiple high-performance designs at 5nm and 4nm nodes through power and area optimization. • Optimized timing closure across multiple clock domains, reducing clock tree insertion delay and improving performance. • Collaborated with cross-functional teams to integrate IP blocks into top-level designs, maintaining cohesive development and on-time delivery. • Automated design tasks with advanced scripting (TCL, Python), reducing manual effort by 20% and improving workflow efficiency. • Directed IP’s sign-off, including IR target setting, power grid exploration, and switch placement strategies to mitigate IR drop and electromigration. • Partnered with logic design teams to drive early physical design aspects, meeting critical schedules and design goals. • Conducted PPA exploration for GPU blocks, identifying and executing optimal solutions to enhance design performance. • Resolved routing congestion, cell/pin density issues, and timing-critical paths with creative, effective solutions to ensure robust designs. • Mentored and coached new team members, providing technical direction to ensure successful project outcomes.

• Led the Graphics IP in resolving netlist quality issues by implementing effective strategies for fixing violations. • Executed PnR for a graphics partition, covering synthesis, floor planning, CTS, routing, STA timing, and physical verification. • Performed and resolved lower power checks, SDC lint checks, and LEC, ensuring design accuracy and compliance. • Developed and implemented timing ECOs for the partition, improving timing closure and overall design performance. • Created custom scripts to reduce shorts and congestion, enhancing design quality and efficiency. • Worked on Dual Voltage Frequency Scaling (DVFS) and multi-voltage blocks, executing PnR with DFT and SAIF for robust power management and functionality.

EE LAB Assistant

• Worked on ASIC Physical Design flow, block-level implementation with multi-clock and multiple macro placements in TSMC 28nm. • Implemented RTL to GDS II: Block level implementation of 32-bit RISC CORE processor • Initialized steps of building the library and setting up the tool to place and route. Experimented with different floorplans, ports, macro positions, route and post route flows. • Fixed congestions at VA boundary and macro edges. • Built a Clock tree to optimize skew, Insertion delay & power.