Kishan Joshi

Design engineer with focus on low power, low noise and high power supply ripple rejection circuit design and power management circuits including linear-low dropout regulators. Experience includes design of blocks of LDOs including subregulators, current limit, error amplifier along with top level integration, leading design end-to-end

May'16 - May'18 Design of a wideband high PSR, ultra low Iq LDO for 1-4V output and load current upto 250mA. The LDO consists of adaptive and dynamic biasing schemes to improve the transient performance and provides high PSR across a wide bandwidth. Feb'16 - Dec'17 Design of an mixed-mode adaptive ripple canceller for Buck converters. The system senses the ripple on the output of the DCDC converter and generates an inverse ripple cancellation current and provides ~26dB of ripple cancellation. Feb'15 - May'16 Design of 4phase Buck Converter for 1-4V output range and load current of 10A with switching frequency of 5MHz. The Buck converter includes load shedding, DCM modes and current sharing between phases.

Worked on ultra-low power Linear Low-Dropout Regulators (LDOs). Challenges included doing ultra-low power design with tight specification control

Developed a robust statistical simulation technique for Analog/MS IP. Worked on Continuous-time sigma-delta converters to arrive at better accuracy Monte Carlo simulation results with lesser number of samples.

Worked on ringing mitigation techniques for high switching frequency, medium power DC DC converters on 130nm technology. Developed an innovative 4-level architecture for step-down converters and compared the impact of architectures on ringing performance due to parasitics.

Schematic design, characterization of liberty timing data (in Cadence Altos), standard cell layouts, VerilogAMS & verilog support for libraries, synthesis of 75K-120K gate designs targeted for high porosity/low power

Specialization in Analog & Mixed-Signal VLSI design with focus on low power DC-DC converters, Phase locked loops.