Kiran Keshav

Performed validation and bring-up of AMD Instinct (MI) and NAVI GPU platforms, ensuring stable firmware and hardware integration across large-scale compute systems. Worked in a data center lab environment, managing large-scale GPU clusters, server racks, and interconnect systems for compute and AI validation workloads. Took part in a large-scale system migration project, coordinating downtime scheduling, applying DHCP/IP provisioning, configuring IPMI access, and validating network connectivity across new infrastructure. Configured and managed PiKVM Pro units to enable remote IPMI control, power cycling, BIOS access, and firmware flashing across distributed GPU systems. Installed and validated RDIMMs and NVMe storage during platform bring-up, verifying slot configuration, link integrity, and system stability under Linux and UEFI environments. Utilized oscilloscopes, logic analyzers, and JTAG tools for board-level power, signal integrity, and fault isolation debugging. Collaborated with firmware and embedded systems teams to debug power sequencing, performance anomalies, and DDR/PCIe interface-level issues. Conducted power and performance characterization under varying workloads, correlating SoC telemetry data with lab measurements to evaluate platform efficiency. Designed and deployed automated validation pipelines using Jenkins and Ansible, reducing manual test overhead and improving execution efficiency. Engaged in cross-functional collaboration with silicon design, validation, and system teams to enhance platform reliability, RAS coverage, and post-silicon readiness. Gained deep exposure to data center GPU infrastructure, DDR RAS validation, and firmware-level diagnostics across Ubuntu, RHEL, and SLES systems.

Supported embedded SoC validation for infotainment ECUs, focusing on power delivery, timing synchronization, and interface-level debug (CAN, I2C, SPI). Executed ATE-style validation and functional pattern testing, contributing to test development and production-level test coverage for ECU boards. Assisted with Design-for-Test (DFT) analysis using boundary-scan (JTAG) methodologies for post-flash verification and board-level fault localization. Performed power integrity and timing correlation analysis across hardware subsystems to evaluate regulator stability and performance margins. Developed Python automation scripts for test log parsing, voltage/current telemetry capture, and trend reporting, improving validation throughput and diagnostic accuracy. Collaborated with cross-functional hardware and manufacturing teams to analyze Power, Performance, and Area (PPA) trade-offs and implement test optimization strategies. Contributed to test fixture design and diagnostic tool refinement, enabling reproducible validation flows and improved test efficiency across multiple ECU variants.

Fundamentals of Digital Design and Computer Organization • Assisted in testing and debugging of digital IC designs, including a single-cycle MIPS processor using Xilinx Vivado with Verilog/System Verilog. • Conducted functional validation and hardware testing of circuits on TUL PYNQ Z2 FPGA, focusing on stability and signal integrity. • Managed course delivery, hosted office hours, and provided hands-on lab support to students, deepening their understanding of digital hardware design.

• Designed and implemented a Multi-layer Reversible ALU using Xilinx ISE, Pspice, and QCA technology, incorporating Mathcad for initial modeling and power efficiency. • Conducted RTL synthesis, debugging, and schematic analysis with a focus on silicon stability and optimization for power-sensitive applications. • Presented research findings at the university Research Symposium, highlighting advancements in reversible logic design and power conservation.

VLSI Design, Analog Integrated Circuit Design, Computer Architecture, Fundamentals of Computer Engineering.