Kevin Tang

Lead the research and development of next-generation DNA sequencing chips for the biotechnology industry, integrate system architecture, sensor design and mass production testing, and promote the commercialization of cutting-edge genomic technologies.

Developing next-generation DNA sequencing chips for the biotechnology industry.Developing next-generation DNA sequencing chips for the biotechnology industry

At Cypress Semiconductor, I served as Product and Test Engineering Manager for multiple chip families, including SRAM, DRAM, image sensors, and mixed-signal analog microcontrollers. I was responsible for product DFT/DFM, qualification, characterization, production test development, and customer returns. I led hardware and manufacturing development of test benches and production test boards for mixed-signal, SRAM, DRAM, PSRAM memories, and CMOS image sensors, focusing on power distribution, signal integrity, and component selection. Managed 6 to 7 designs annually, with budgets ranging from $5K to $200K each. Oversaw selection, procurement, installation, and ramp-up of production testers, managing vendor roadmaps, total cost of ownership, and unit production costs. Successfully launched five tester platforms, including Advantest, Verigy 93K, and Nextest. Handled subcontractor selection, auditing, contract negotiation, and cost control for wafer and package testing, enabling volume manufacturing in the US, Taiwan, and the Philippines. Developed production and characterization test programs for PSOC (analog mixed-signal embedded microcontrollers), SRAM, DRAM, PSRAM, and CMOS image sensors. Designed and implemented a Test Program Management System covering change control, content validation, and deployment for approximately 6,000 part numbers, reducing test program revision errors to zero. Implemented a modular block-based test development methodology to facilitate peer code reviews, code reuse, and parallel development. Built and scaled product and test engineering teams in Taiwan and San Jose from 4 to 15 engineers within 2.5 years (9 in Taiwan, 6 in the US), and shortened silicon debug cycle time from 8 weeks to 2 weeks