Keerthi Patil

I am a recent Master’s graduate in Electrical Engineering (MSEE) with hands-on experience in RTL design, design verification, and digital hardware development. My focus is on building functionally correct, scalable, and verifiable hardware, and I am motivated by work that directly impacts real silicon and deployed systems. I bring practical experience in SystemVerilog-based verification and RTL development (Verilog/VHDL), having worked on UART, FIFO, memory controllers, and AMBA APB interfaces. My background also includes FPGA-based implementation and validation, along with embedded system development using STM32 microcontrollers, giving me exposure to both hardware and hardware-software interaction. I have implemented testbenches, assertions, and functional coverage, and performed waveform-driven debug using industry-standard EDA tools. I also have strong exposure to processor-centric design, including a RISC-V processor and a custom 8-bit RISC CPU designed at the transistor level in 45 nm technology. In addition to hands-on project work, I have experience reviewing digital designs and mentoring peers, which strengthened my ability to interpret specifications, identify functional corner cases, and communicate technical findings clearly. I am actively seeking entry-level full-time opportunities in Design Verification, RTL/Digital Design, or VLSI/SoC engineering, where I can contribute strong fundamentals, disciplined engineering practices, and a strong ownership mindset.