Karthik Patil
AMS Verification Engineer @ Iravan Technologies
About
AMS Verification Engineer with experience in Co-Simulation, behavioral modeling, and verification of high-speed SerDes PHYs and memory interfaces. Worked on multi-protocol SerDes verification supporting PCIe, SATA, Ethernet, and CCIX, including PLL/CDR validation and PVT-corner analysis. Currently working on HBM verification. Hands-on experience in Verilog-AMS, SV-RNM, Wreal modeling, AMS assertions, and Model vs Schematic (MVS) validation for analog IPs including POR, SAR ADC, LDO, and VCO. Technical interests: AMS Verification, Behavioral Modeling, Verilog-AMS, UVM-MS, HBM/DDR, SerDes PHY, PLL/CDR, and Mixed-Signal SoC Verification.
India
Bengaluru
Semiconductors
Verilog-AMS, analog modelling, Real Number modelling, SVRNM, AMBA AHB, Code Coverage, Scripting, Cadence Virtuoso, Spyglass, SerDes, AMS verification, Linux, Synopsys tools, vcs, Mixed-Signal IC Design, Python scripting , USB3.0, Service Provider Interface (SPI), Teamwork, Remote Work
Experience

AMS Verification Engineer
Pune City, Maharashtra, India
AMS Verification Engineer at IRAVAN Technologies, working on Analog Mixed-Signal (AMS) verification of high-speed and power management IPs at both block and system level. Experienced in developing and validating SystemVerilog RNM (SV-RNM) and Verilog-AMS behavioral models for analog components including ADC, LDO, VCO, and POR. Skilled in performing Model vs Schematic (MVS) correlation across PVT corners to ensure alignment with transistor-level simulations. Proficient in building and executing AMS/UVM-based testbenches, incorporating assertions and self-checkers for robust functional and corner-case validation. Hands-on experience in debugging mixed-signal issues using waveform analysis tools such as SimVision, with a strong focus on root-cause identification across analog and digital domains. Actively involved in co-simulation and system-level verification, enabling faster regression cycles and improved coverage through RNM methodologies. Collaborating closely with design and integration teams to resolve functional, modeling, and convergence issues, while supporting large-scale regressions and verification closure in SoC environments.

AMS verification Engineer (GET)
Bengaluru, Karnataka, India
Worked on Highspeed SerDes PHY IP in IPG group at Synopsys. • Responsible for handling RTL and Analog verification, primarily between PCS and PMA of SerDes • Responsible for carrying out functional verification of multi-protocol SerDes PHY which supports PCIE (gen 1-5), SATA, Ethernet, CCIX and SGMI protocol. • Executed 50+ simulations across SS, TT, and FF corners for TX, RX, and support blocks, verifying functionality and extracting detailed power metrics for each block. • Performed GLS verification with SDF, ensuring timing and functional correctness. • Using the extracted netlist, developed the testbench and environment setup for various test cases such as data rate change, power analysis and FSM evaluation of the top-level module of the PHY
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